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Searched refs:UVD_HWIP (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Damdgpu_discovery.c184 [UVD_HWIP] = UVD_HWID,
269 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && in amdgpu_discovery_harvest_config_quirk()
1851 switch (adev->ip_versions[UVD_HWIP][0]) { in amdgpu_discovery_set_mm_ip_blocks()
1861 adev->ip_versions[UVD_HWIP][0]); in amdgpu_discovery_set_mm_ip_blocks()
1878 switch (adev->ip_versions[UVD_HWIP][0]) { in amdgpu_discovery_set_mm_ip_blocks()
1923 adev->ip_versions[UVD_HWIP][0]); in amdgpu_discovery_set_mm_ip_blocks()
1990 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2012 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2035 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); in amdgpu_discovery_set_ip_blocks()
2051 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); in amdgpu_discovery_set_ip_blocks()
[all …]
Darct_reg_init.c41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in arct_reg_base_init()
Dvega10_reg_init.c41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega10_reg_base_init()
Dvega20_reg_init.c41 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i])); in vega20_reg_base_init()
Damdgpu_vcn.c99 switch (adev->ip_versions[UVD_HWIP][0]) { in amdgpu_vcn_sw_init()
259 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)){ in amdgpu_vcn_sw_init()
349 if (adev->ip_versions[UVD_HWIP][0] >= IP_VERSION(4, 0, 0)) in amdgpu_vcn_using_unified_queue()
Dvcn_v3_0.c102 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 0, 33)) in vcn_v3_0_early_init()
227 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 2)) in vcn_v3_0_sw_init()
229 else if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(3, 1, 1)) in vcn_v3_0_sw_init()
1257 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { in vcn_v3_0_start()
1630 if (adev->ip_versions[UVD_HWIP][0] != IP_VERSION(3, 0, 33)) { in vcn_v3_0_pause_dpg_mode()
Djpeg_v3_0.c55 switch (adev->ip_versions[UVD_HWIP][0]) { in jpeg_v3_0_early_init()
Damdgpu_uvd.c1142 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; in amdgpu_uvd_send_msg()
1143 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; in amdgpu_uvd_send_msg()
Damdgpu.h658 UVD_HWIP, enumerator
659 VCN_HWIP = UVD_HWIP,
Dsoc21.c80 switch (adev->ip_versions[UVD_HWIP][0]) { in soc21_query_video_codecs()
Duvd_v7_0.c1297 reg -= p->adev->reg_offset[UVD_HWIP][0][1]; in uvd_v7_0_ring_patch_cs_in_place()
1298 reg += p->adev->reg_offset[UVD_HWIP][1][1]; in uvd_v7_0_ring_patch_cs_in_place()
Dnv.c184 switch (adev->ip_versions[UVD_HWIP][0]) { in nv_query_video_codecs()
Dvcn_v2_5.c1725 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) in vcn_v2_5_set_dec_ring_funcs()
1742 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)) in vcn_v2_5_set_enc_ring_funcs()
Dsoc15.c172 switch (adev->ip_versions[UVD_HWIP][0]) { in soc15_query_video_codecs()
Damdgpu_ucode.c1081 case UVD_HWIP: in amdgpu_ucode_ip_version_decode()
Damdgpu_kms.c498 result->ip_discovery_version = adev->ip_versions[UVD_HWIP][0]; in amdgpu_hw_ip_info()