Searched refs:UCR1_RRDYEN (Results 1 – 1 of 1) sorted by relevance
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ macro414 ucr1 |= UCR1_RRDYEN; in imx_uart_start_rx()501 ucr1 &= ~UCR1_RRDYEN; in imx_uart_stop_rx()952 if ((ucr1 & UCR1_RRDYEN) == 0) in imx_uart_int()1441 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN; in imx_uart_startup()1493 ucr1 |= UCR1_RRDYEN; in imx_uart_startup()1554 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN); in imx_uart_shutdown()1861 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN); in imx_uart_poll_init()1870 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); in imx_uart_poll_init()2001 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN); in imx_uart_console_write()[all …]