Searched refs:SSCR0_SSE (Results 1 – 5 of 5) sorted by relevance
139 Ser4SSCR0 |= SSCR0_SSE; in ssp_enable()149 Ser4SSCR0 &= ~SSCR0_SSE; in ssp_disable()163 Ser4SSCR0 &= ~SSCR0_SSE; in ssp_save_state()176 Ser4SSCR0 = ssp->cr0 & ~SSCR0_SSE; in ssp_restore_state()222 Ser4SSCR0 &= ~SSCR0_SSE; in ssp_exit()
56 #define SSCR0_SSE BIT(7) /* Synchronous Serial Port Enable */ macro278 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) | SSCR0_SSE; in pxa_ssp_enable()286 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~SSCR0_SSE; in pxa_ssp_disable()
145 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0); in pxa_ssp_resume()557 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) in pxa_ssp_hw_params()689 if (value && (sscr0 & SSCR0_SSE)) in pxa_ssp_set_running_bit()690 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE); in pxa_ssp_set_running_bit()709 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE); in pxa_ssp_set_running_bit()
46 | SSCR0_SSE /* SSE = 1; SSP enabled */233 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { in navpoint_probe()
770 #define SSCR0_SSE 0x00000080 /* SSP Enable */ macro