Searched refs:SDMA0_HWIP (Results 1 – 17 of 17) sorted by relevance
399 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); in sdma_v4_0_get_reg_offset()472 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_golden_registers()542 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_setup_ulv()584 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_microcode()624 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || in sdma_v4_0_init_microcode()625 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { in sdma_v4_0_init_microcode()1024 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && in sdma_v4_0_ctx_switch_enable()1305 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_pg()1748 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_fw_support_paging_queue()1773 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && in sdma_v4_0_early_init()[all …]
174 [SDMA0_HWIP] = SDMA0_HWID,1806 switch (adev->ip_versions[SDMA0_HWIP][0]) { in amdgpu_discovery_set_sdma_ip_blocks()1842 adev->ip_versions[SDMA0_HWIP][0]); in amdgpu_discovery_set_sdma_ip_blocks()1980 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()2002 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()2026 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()2042 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()2063 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()2087 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); in amdgpu_discovery_set_ip_blocks()2115 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()[all …]
46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
43 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in aldebaran_reg_base_init()
44 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in arct_reg_base_init()
47 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in vega10_reg_base_init()
40 uint32_t sdma_base = adev->reg_offset[SDMA0_HWIP][0][0]; in sdma_v4_4_get_reg_offset()
46 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i])); in vega20_reg_base_init()
111 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_init_microcode()1582 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_clock_gating()1619 …if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2,… in sdma_v5_2_update_medium_grain_light_sleep()1648 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_2_set_clockgating_state()
187 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_golden_registers()245 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) in sdma_v5_0_init_microcode()250 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_init_microcode()1729 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v5_0_set_clockgating_state()
644 SDMA0_HWIP, enumerator
1072 case SDMA0_HWIP: in amdgpu_ucode_ip_version_decode()
182 if (adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(6, 0, 0)) in amdgpu_mes_init()
97 amdgpu_ucode_ip_version_decode(adev, SDMA0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in sdma_v6_0_init_microcode()
493 result->ip_discovery_version = adev->ip_versions[SDMA0_HWIP][0]; in amdgpu_hw_ip_info()
184 return dev->adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(5, 2, 0); in pm_use_ext_eng()
66 uint32_t sdma_version = kfd->adev->ip_versions[SDMA0_HWIP][0]; in kfd_device_info_set_sdma_info()