| /linux-6.1.9/include/dt-bindings/clock/ |
| D | rk3036-cru.h | 25 #define SCLK_UART2 79 macro
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| D | exynos7-clk.h | 97 #define SCLK_UART2 5 macro
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| D | s5pv210.h | 195 #define SCLK_UART2 173 macro
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| D | rk3188-cru-common.h | 22 #define SCLK_UART2 66 macro
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| D | rk3128-cru.h | 27 #define SCLK_UART2 79 macro
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| D | rk3228-cru.h | 26 #define SCLK_UART2 79 macro
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| D | rv1108-cru.h | 24 #define SCLK_UART2 74 macro
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| D | rk3288-cru.h | 34 #define SCLK_UART2 79 macro
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| D | rk3308-cru.h | 23 #define SCLK_UART2 19 macro
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| D | rk3328-cru.h | 29 #define SCLK_UART2 40 macro
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| D | rk3368-cru.h | 32 #define SCLK_UART2 79 macro
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| D | px30-cru.h | 27 #define SCLK_UART2 25 macro
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| D | rockchip,rv1126-cru.h | 86 #define SCLK_UART2 20 macro
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| D | rk3399-cru.h | 40 #define SCLK_UART2 83 macro
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| D | rk3568-cru.h | 354 #define SCLK_UART2 291 macro
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| /linux-6.1.9/drivers/clk/rockchip/ |
| D | clk-rk3036.c | 158 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3128.c | 194 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3228.c | 208 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3188.c | 268 MUX(SCLK_UART2, "sclk_uart2", mux_sclk_uart2_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3328.c | 261 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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| D | clk-rv1108.c | 176 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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| D | clk-rk3368.c | 409 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-s5pv210.c | 596 GATE(SCLK_UART2, "sclk_uart2", "dout_uart2", CLK_SRC_MASK0, 14,
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| /linux-6.1.9/arch/arm/boot/dts/ |
| D | rk3xxx.dtsi | 424 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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| D | s5pv210.dtsi | 344 <&clocks SCLK_UART2>;
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