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Searched refs:R5 (Results 1 – 25 of 42) sorted by relevance

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/linux-6.1.9/arch/arm64/boot/dts/ti/
Dk3-am62a.dtsi83 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
84 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
85 <0x00 0x79100000 0x00 0x79100000 0x00 0x00040000>, /* MCU R5 IRAM0 */
86 <0x00 0x79140000 0x00 0x79140000 0x00 0x00040000>, /* MCU R5 IRAM1 */
92 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM */
93 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM */
100 <0x00 0x79000000 0x00 0x79000000 0x00 0x00008000>, /* MCU R5 ATCM */
101 <0x00 0x79020000 0x00 0x79020000 0x00 0x00008000>, /* MCU R5 BTCM */
113 <0x00 0x78000000 0x00 0x78000000 0x00 0x00008000>, /* DM R5 ATCM*/
114 <0x00 0x78100000 0x00 0x78100000 0x00 0x00008000>; /* DM R5 BTCM*/
/linux-6.1.9/drivers/tty/serial/
Dpmac_zilog.c135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); in pmz_load_zsregs()
167 write_zsreg(uap, R5, regs[R5]); in pmz_load_zsregs()
554 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
555 uap->curregs[R5] &= ~clear_bits; in pmz_set_mctrl()
557 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_set_mctrl()
559 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
692 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
693 if (new_reg != uap->curregs[R5]) { in pmz_break_ctl()
694 uap->curregs[R5] = new_reg; in pmz_break_ctl()
695 write_zsreg(uap, R5, uap->curregs[R5]); in pmz_break_ctl()
[all …]
Dip22zilog.c188 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
221 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
561 up->curregs[R5] |= set_bits; in ip22zilog_set_mctrl()
562 up->curregs[R5] &= ~clear_bits; in ip22zilog_set_mctrl()
563 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_set_mctrl()
671 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in ip22zilog_break_ctl()
672 if (new_reg != up->curregs[R5]) { in ip22zilog_break_ctl()
673 up->curregs[R5] = new_reg; in ip22zilog_break_ctl()
676 write_zsreg(channel, R5, up->curregs[R5]); in ip22zilog_break_ctl()
726 up->curregs[R5] |= TxENAB; in __ip22zilog_startup()
[all …]
Dsunzilog.c207 write_zsreg(channel, R5, regs[R5] & ~TxENAB); in __load_zsregs()
254 write_zsreg(channel, R5, regs[R5]); in __load_zsregs()
661 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
662 up->curregs[R5] &= ~clear_bits; in sunzilog_set_mctrl()
663 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_set_mctrl()
771 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
772 if (new_reg != up->curregs[R5]) { in sunzilog_break_ctl()
773 up->curregs[R5] = new_reg; in sunzilog_break_ctl()
776 write_zsreg(channel, R5, up->curregs[R5]); in sunzilog_break_ctl()
791 up->curregs[R5] |= TxENAB; in __sunzilog_startup()
[all …]
Dzs.c270 write_zsreg(zport, R5, regs[5] & ~TxENAB); in load_zsregs()
285 write_zsreg(zport, R5, regs[5]); in load_zsregs()
402 write_zsreg(zport_a, R5, zport_a->regs[5]); in zs_set_mctrl()
526 write_zsreg(zport, R5, zport->regs[5]); in zs_break_ctl()
791 write_zsreg(zport, R5, zport->regs[5]); in zs_startup()
815 write_zsreg(zport, R5, zport->regs[5]); in zs_shutdown()
972 write_zsreg(zport, R5, zport->regs[5]); in zs_pm()
1165 write_zsreg(zport, R5, zport->regs[5]); in zs_console_write()
1177 write_zsreg(zport, R5, zport->regs[5]); in zs_console_write()
Dzs.h65 #define R5 5 macro
Dip22zilog.h44 #define R5 5 macro
Dsunzilog.h36 #define R5 5 macro
/linux-6.1.9/tools/perf/arch/arm/tests/
Dregs_load.S9 #define R5 0x28 macro
46 str r5, [r0, #R5]
/linux-6.1.9/tools/perf/arch/powerpc/tests/
Dregs_load.S10 #define R5 5 * 8 macro
49 std 5, R5(3)
/linux-6.1.9/lib/
Dtest_bpf.c44 #define R5 BPF_REG_5 macro
1623 i += __bpf_ld_imm64(&insns[i], R5, keep); in __bpf_emit_atomic64()
1635 insns[i++] = BPF_JMP_REG(BPF_JEQ, R0, R5, 1); in __bpf_emit_atomic64()
1670 i += __bpf_ld_imm64(&insns[i], R5, keep); in __bpf_emit_atomic32()
1682 insns[i++] = BPF_JMP_REG(BPF_JEQ, R0, R5, 1); in __bpf_emit_atomic32()
3783 BPF_ALU64_IMM(BPF_MOV, R5, 5),
3793 BPF_ALU64_IMM(BPF_ADD, R5, 20),
3803 BPF_ALU64_IMM(BPF_SUB, R5, 10),
3813 BPF_ALU64_REG(BPF_ADD, R0, R5),
3825 BPF_ALU64_REG(BPF_ADD, R1, R5),
[all …]
/linux-6.1.9/arch/powerpc/platforms/pseries/
DhvCall.S36 std r5,STK_PARAM(R5)(r1); \
48 ld r5,STACK_FRAME_OVERHEAD+STK_PARAM(R5)(r1); \
183 HCALL_INST_PRECALL(R5)
295 HCALL_INST_PRECALL(R5)
/linux-6.1.9/arch/hexagon/kernel/
Dvm_entry.S57 { memd(R0 + #_PT_R0504) = R5:4; \
100 memd(R0 + #_PT_R0504) = R5:4; \
136 { R5:4 = memd(R0 + #_PT_R0504); \
168 { R5:4 = memd(R0 + #_PT_R0504); \
/linux-6.1.9/arch/s390/crypto/
Dcrc32le-vx.S66 .octa 0x163cd6124 # R5
74 .octa 0x0dd45aab8 # R5
Dcrc32be-vx.S64 .quad 0x0f200aa66, 1 << 32 # R5, x32
/linux-6.1.9/drivers/net/hamradio/
Dscc.c805 wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */ in init_channel()
937 or(scc,R5, TxENAB); in scc_key_trx()
938 scc->wreg[R5] |= RTS; in scc_key_trx()
940 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ in scc_key_trx()
943 cl(scc,R5,RTS|TxENAB); in scc_key_trx()
971 or(scc,R5, TxENAB); in scc_key_trx()
972 scc->wreg[R5] |= RTS; in scc_key_trx()
974 or(scc,R5,RTS|TxENAB); /* enable tx */ in scc_key_trx()
977 cl(scc,R5,RTS|TxENAB); /* disable tx */ in scc_key_trx()
1110 if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) ) in is_grouped()
[all …]
Dz8530.h12 #define R5 5 macro
/linux-6.1.9/Documentation/bpf/
Dclassic_vs_extended.rst30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
65 place function arguments into R1 to R5 registers to satisfy calling
67 to in-kernel function. If R1 - R5 registers are mapped to CPU registers
74 After an in-kernel function call, R1 - R5 are reset to unreadable and R0 has
123 R5 - r8
139 bpf_mov R5, 5
146 bpf_mov R5, 9
188 interpreter. R0-R5 are scratch registers, so eBPF program needs to preserve
198 After the call the registers R1-R5 contain junk values and cannot be read.
Dverifier.rst32 After kernel function call, R1-R5 are reset to unreadable and
219 R1=ctx R3=pkt(id=0,off=0,r=14) R4=pkt_end R5=pkt(id=0,off=14,r=14) R10=fp
230 Note that R5 is marked as R5=pkt(id=0,off=14,r=14). It also points
232 it now points to ``skb->data + 14`` and accessible range is [R5, R5 + 14 - 14)
238 R0=inv1 R1=ctx R3=pkt(id=0,off=0,r=14) R4=pkt_end R5=pkt(id=0,off=14,r=14) R10=fp
252 … R3=pkt(id=2,off=0,r=8) R4=inv(id=0,umax_value=3570,var_off=(0x0; 0xfffe)) R5=pkt(id=0,off=14,r=14…
Dlinux-notes.rst38 * Registers R1-R5 are scratch registers that are clobbered by the
/linux-6.1.9/drivers/media/i2c/
Dwm8739.c36 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator
222 wm8739_write(sd, R5, 0x000); in wm8739_probe()
/linux-6.1.9/tools/perf/arch/arm/util/
Dunwind-libdw.c24 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux-6.1.9/arch/hexagon/lib/
Dmemcpy.S164 #define ptr_in_p_128 R5 /* pointer for prefetch of input data */
167 #define shift2 R5 /* in epilog to workshifter to extract bytes */
177 #define ptr_in_p_128kernel R5:4 /* packed fetch pointer & kernel cnt */
/linux-6.1.9/tools/perf/arch/s390/util/
Dunwind-libdw.c29 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()
/linux-6.1.9/tools/perf/arch/powerpc/util/
Dunwind-libdw.c33 dwarf_regs[5] = REG(R5); in libdw__arch_set_initial_registers()

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