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Searched refs:PLL1 (Results 1 – 16 of 16) sorted by relevance

/linux-6.1.9/sound/soc/codecs/ !
Dak4642.c115 #define PLL1 (1 << 5) macro
117 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
351 pll = PLL2 | PLL1; in ak4642_dai_set_sysclk()
354 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
367 pll = PLL3 | PLL2 | PLL1; in ak4642_dai_set_sysclk()
371 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
/linux-6.1.9/Documentation/devicetree/bindings/clock/ !
Dmicrochip,mpfs-ccc.yaml25 - description: PLL1's control registers
37 - description: PLL1's refclk0
38 - description: PLL1's refclk1
Dti,cdce925.txt30 For all PLL1, PLL2, ... an optional child node can be used to specify spread
Dst,nomadik.txt30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
/linux-6.1.9/Documentation/arm/sunxi/ !
Dclocks.rst20 PLL1
31 PLL1 |
/linux-6.1.9/include/dt-bindings/clock/ !
Dqcom,mmcc-msm8960.h126 #define PLL1 117 macro
Dstm32mp13-clks.h19 #define PLL1 6 macro
Dstm32mp1-clks.h183 #define PLL1 176 macro
/linux-6.1.9/Documentation/devicetree/bindings/clock/ti/davinci/ !
Dpll.txt10 - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
/linux-6.1.9/Documentation/devicetree/bindings/clock/st/ !
Dst,flexgen.txt31 | | |PLL1 | | | | | | | | | |
/linux-6.1.9/drivers/media/dvb-frontends/ !
Dzl10039.c40 PLL1, enumerator
/linux-6.1.9/arch/arm/boot/dts/ !
Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
/linux-6.1.9/arch/mips/boot/dts/ingenic/ !
Dgcw0.dts442 * Put high-speed peripherals under PLL1, such that we can change the
/linux-6.1.9/drivers/clk/nxp/ !
Dclk-lpc18xx-cgu.c519 LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
/linux-6.1.9/drivers/clk/ !
DKconfig201 Y2 and Y3 derive from PLL1
Dclk-stm32mp1.c1773 PLL(PLL1, "pll1", ref12_parents, 0, RCC_PLL1CR, RCC_RCK12SELR),
2093 PLL1,