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Searched refs:MS (Results 1 – 25 of 79) sorted by relevance

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/linux-6.1.9/drivers/net/wireless/ath/ath9k/
Dar9003_mac.c288 MS(s5, AR_ISR_S5_GENTIMER_TRIG); in ar9003_hw_get_isr()
291 MS(s5, AR_ISR_S5_GENTIMER_THRESH); in ar9003_hw_get_isr()
369 if ((MS(ads->ds_info, AR_DescId) != ATHEROS_VENDOR_ID) || in ar9003_hw_proc_txdesc()
370 (MS(ads->ds_info, AR_TxRxDesc) != 1)) { in ar9003_hw_proc_txdesc()
377 ts->ts_rateindex = MS(status, AR_FinalTxIdx); in ar9003_hw_proc_txdesc()
378 ts->ts_seqnum = MS(status, AR_SeqNum); in ar9003_hw_proc_txdesc()
379 ts->tid = MS(status, AR_TxTid); in ar9003_hw_proc_txdesc()
381 ts->qid = MS(ads->ds_info, AR_TxQcuNum); in ar9003_hw_proc_txdesc()
382 ts->desc_id = MS(ads->status1, AR_TxDescId); in ar9003_hw_proc_txdesc()
390 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); in ar9003_hw_proc_txdesc()
[all …]
Dar9002_mac.c123 ah->intr_txqs = MS(s0_s, AR_ISR_S0_QCU_TXOK); in ar9002_hw_get_isr()
124 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC); in ar9002_hw_get_isr()
125 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR); in ar9002_hw_get_isr()
126 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL); in ar9002_hw_get_isr()
147 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG); in ar9002_hw_get_isr()
150 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH); in ar9002_hw_get_isr()
332 ts->tid = MS(status, AR_TxTid); in ar9002_hw_proc_txdesc()
333 ts->ts_rateindex = MS(status, AR_FinalTxIdx); in ar9002_hw_proc_txdesc()
334 ts->ts_seqnum = MS(status, AR_SeqNum); in ar9002_hw_proc_txdesc()
337 ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); in ar9002_hw_proc_txdesc()
[all …]
Dar9003_aic.c283 MS(value, AR_PHY_AIC_SRAM_VALID); in ar9003_aic_cal_post_process()
285 MS(value, AR_PHY_AIC_SRAM_ROT_QUAD_ATT_DB); in ar9003_aic_cal_post_process()
287 MS(value, AR_PHY_AIC_SRAM_VGA_QUAD_SIGN); in ar9003_aic_cal_post_process()
289 MS(value, AR_PHY_AIC_SRAM_ROT_DIR_ATT_DB); in ar9003_aic_cal_post_process()
291 MS(value, AR_PHY_AIC_SRAM_VGA_DIR_SIGN); in ar9003_aic_cal_post_process()
293 MS(value, AR_PHY_AIC_SRAM_COM_ATT_6DB); in ar9003_aic_cal_post_process()
387 fixed_com_att_db = com_att_db_table[MS(aic->aic_sram[i], in ar9003_aic_cal_post_process()
459 num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN); in ar9003_aic_cal_continue()
587 num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN); in ar9003_aic_calibration_single()
Dar5008_phy.c1142 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); in ar5008_hw_do_getnf()
1145 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); in ar5008_hw_do_getnf()
1148 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); in ar5008_hw_do_getnf()
1154 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1157 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1160 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); in ar5008_hw_do_getnf()
1186 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); in ar5008_hw_ani_cache_ini_regs()
1187 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); in ar5008_hw_ani_cache_ini_regs()
1188 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); in ar5008_hw_ani_cache_ini_regs()
1191 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); in ar5008_hw_ani_cache_ini_regs()
[all …]
Dar9003_phy.c1352 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1359 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1410 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1411 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1412 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); in ar9003_hw_ani_cache_ini_regs()
1415 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1416 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1417 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); in ar9003_hw_ani_cache_ini_regs()
1420 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1421 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
[all …]
Dmac.c115 curLevel = MS(txcfg, AR_FTRIG); in ath9k_hw_updatetxtriglevel()
553 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined); in ath9k_hw_rxprocdesc()
554 rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0, in ath9k_hw_rxprocdesc()
556 rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0, in ath9k_hw_rxprocdesc()
558 rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0, in ath9k_hw_rxprocdesc()
560 rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4, in ath9k_hw_rxprocdesc()
562 rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4, in ath9k_hw_rxprocdesc()
564 rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4, in ath9k_hw_rxprocdesc()
568 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx); in ath9k_hw_rxprocdesc()
572 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate); in ath9k_hw_rxprocdesc()
[all …]
Dar9002_phy.c298 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), in ar9002_olc_init()
336 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); in ar9002_hw_do_getnf()
339 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
346 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); in ar9002_hw_do_getnf()
349 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); in ar9002_hw_do_getnf()
Dar9002_calib.c383 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); in ar9287_hw_olc_temp_compensation()
413 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT); in ar9280_hw_olc_temp_compensation()
506 regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9), in ar9271_hw_pa_cal()
586 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); in ar9285_hw_pa_cal()
601 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
608 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); in ar9285_hw_pa_cal()
610 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); in ar9285_hw_pa_cal()
611 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); in ar9285_hw_pa_cal()
804 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7), in ar9285_hw_clc()
Dar9003_mci.c832 thresh = MS(mci->config, ATH_MCI_CONFIG_AGGR_THRESH); in ar9003_mci_osla_setup()
944 u8 ant = MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH); in ar9003_mci_reset()
982 regval = MS(mci->config, ATH_MCI_CONFIG_CLK_DIV); in ar9003_mci_reset()
1307 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); in ar9003_mci_state()
1315 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), in ar9003_mci_state()
1321 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), in ar9003_mci_state()
1445 bt_sleep = MS(REG_READ(ah, AR_MCI_RX_STATUS), AR_MCI_RX_REMOTE_SLEEP); in ar9003_mci_set_power_awake()
1466 offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); in ar9003_mci_check_gpm_offset()
1493 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); in ar9003_mci_get_next_gpm_offset()
Dar9003_mci.h122 ((MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
123 (MS(mci->config, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
/linux-6.1.9/Documentation/sound/cards/
Dserial-u16550.rst8 * 1 - Midiator MS-124T support (1)
9 * 2 - Midiator MS-124W S/A mode (2)
10 * 3 - MS-124W M/B mode support (3)
13 For the Midiator MS-124W, you must set the physical M-S and A-B
36 In MS-124T mode, one raw MIDI substream is supported (midiCnD0); the outs
41 Usage example for MS-124T, with A-B switch in A position:
48 In MS-124W S/A mode, one raw MIDI substream is supported (midiCnD0);
58 In MS-124W M/B mode, the driver supports 16 ALSA raw MIDI substreams;
75 The MS-124W hardware's M/A mode is currently not supported. This mode allows
82 Midiator models other than MS-124W and MS-124T are currently not supported.
[all …]
/linux-6.1.9/arch/mips/cavium-octeon/executive/
Dcvmx-spi.c204 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_reset_cb() local
218 __delay(10 * MS); in cvmx_spi_reset_cb()
268 __delay(100 * MS); in cvmx_spi_reset_cb()
275 __delay(100 * MS); in cvmx_spi_reset_cb()
435 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_clock_detect_cb() local
442 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; in cvmx_spi_clock_detect_cb()
467 timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; in cvmx_spi_clock_detect_cb()
512 uint64_t MS = cvmx_sysinfo_get()->cpu_clock_hz / 1000; in cvmx_spi_training_cb() local
513 uint64_t timeout_time = cvmx_get_cycle() + 1000ull * MS * timeout; in cvmx_spi_training_cb()
530 __delay(1000 * MS); in cvmx_spi_training_cb()
[all …]
/linux-6.1.9/drivers/net/wireless/ath/ath10k/
Dhw.c625 phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1; in ath10k_hw_qca988x_set_coverage_class()
658 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); in ath10k_hw_qca988x_set_coverage_class()
672 slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT); in ath10k_hw_qca988x_set_coverage_class()
679 ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); in ath10k_hw_qca988x_set_coverage_class()
685 cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS); in ath10k_hw_qca988x_set_coverage_class()
766 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) in ath10k_hw_qca6174_enable_pll_clock()
769 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; in ath10k_hw_qca6174_enable_pll_clock()
836 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) in ath10k_hw_qca6174_enable_pll_clock()
844 if (MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) in ath10k_hw_qca6174_enable_pll_clock()
867 if (!MS(reg_val, RTC_SYNC_STATUS_PLL_CHANGING)) in ath10k_hw_qca6174_enable_pll_clock()
[all …]
Dspectral.c114 fft_sample->relpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB); in ath10k_spectral_process_fft()
115 fft_sample->avgpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB); in ath10k_spectral_process_fft()
117 peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); in ath10k_spectral_process_fft()
119 fft_sample->max_index = MS(reg0, SEARCH_FFT_REPORT_REG0_PEAK_SIDX); in ath10k_spectral_process_fft()
122 total_gain_db = MS(reg0, SEARCH_FFT_REPORT_REG0_TOTAL_GAIN_DB); in ath10k_spectral_process_fft()
123 base_pwr_db = MS(reg0, SEARCH_FFT_REPORT_REG0_BASE_PWR_DB); in ath10k_spectral_process_fft()
132 chain_idx = MS(reg0, SEARCH_FFT_REPORT_REG0_FFT_CHN_IDX); in ath10k_spectral_process_fft()
Dhtt_rx.c406 msdu_len = MS(__le32_to_cpu(rx_desc_msdu_start_common->info0), in ath10k_htt_rx_amsdu_pop()
1003 preamble = MS(info1, RX_PPDU_START_INFO1_PREAMBLE_TYPE); in ath10k_htt_rx_h_rates()
1014 rate = MS(info1, RX_PPDU_START_INFO1_L_SIG_RATE); in ath10k_htt_rx_h_rates()
1133 peer_id = MS(__le32_to_cpu(rxd_mpdu_start->info0), in ath10k_htt_rx_h_peer_channel()
1781 decap = MS(__le32_to_cpu(rxd_msdu_start_common->info1), in ath10k_htt_rx_h_undecap()
1966 enctype = MS(__le32_to_cpu(rxd_mpdu_start->info0), in ath10k_htt_rx_h_mpdu()
2206 decap = MS(__le32_to_cpu(rxd_msdu_start_common->info1), in ath10k_htt_rx_h_unchain()
2261 enctype = MS(__le32_to_cpu(rxd_mpdu_start->info0), in ath10k_htt_rx_validate_amsdu()
2419 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1), in ath10k_htt_rx_pn_check_replay_hl()
2425 if (!MS(rx_desc_info, HTT_RX_DESC_HL_INFO_ENCRYPTED)) in ath10k_htt_rx_pn_check_replay_hl()
[all …]
/linux-6.1.9/drivers/net/wireless/ath/ath6kl/
Dhif.c317 if (MS(ERROR_INT_STATUS_WAKEUP, error_int_status)) in ath6kl_hif_proc_err_intr()
320 if (MS(ERROR_INT_STATUS_RX_UNDERFLOW, error_int_status)) in ath6kl_hif_proc_err_intr()
323 if (MS(ERROR_INT_STATUS_TX_OVERFLOW, error_int_status)) in ath6kl_hif_proc_err_intr()
495 if (MS(HOST_INT_STATUS_CPU, host_int_status)) { in proc_pending_irqs()
502 if (MS(HOST_INT_STATUS_ERROR, host_int_status)) { in proc_pending_irqs()
509 if (MS(HOST_INT_STATUS_COUNTER, host_int_status)) in proc_pending_irqs()
/linux-6.1.9/drivers/gpu/drm/i915/
Di915_utils.h294 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) argument
358 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000) argument
/linux-6.1.9/drivers/gpu/drm/gma500/
Dintel_gmbus.c39 #define _wait_for(COND, MS, W) ({ \ argument
40 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
53 #define wait_for(COND, MS) _wait_for(COND, MS, 1) argument
Dcdv_intel_display.c112 #define _wait_for(COND, MS, W) ({ \ argument
113 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
126 #define wait_for(COND, MS) _wait_for(COND, MS, 1) argument
/linux-6.1.9/drivers/staging/rtl8712/
Drtl8712_wmac_regdef.h26 #define MS (RTL8712_WMAC_ + 0x24) macro
/linux-6.1.9/Documentation/translations/zh_CN/loongarch/
Dbooting.rst39 u32 MZ_MAGIC /* "MZ", MS-DOS 头 */
/linux-6.1.9/sound/soc/codecs/
Dak4642.c85 #define MS (1 << 3) /* master/slave select */ macro
398 data |= MS; in ak4642_dai_set_fmt()
406 snd_soc_component_update_bits(component, PW_MGMT2, MS | MCKO | PMPLL, data); in ak4642_dai_set_fmt()
/linux-6.1.9/drivers/gpu/drm/v3d/
Dv3d_drv.h338 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) argument
/linux-6.1.9/Documentation/loongarch/
Dbooting.rst33 u32 MZ_MAGIC /* "MZ", MS-DOS header */
/linux-6.1.9/Documentation/fault-injection/
Dnvme-fault-injection.rst143 Hardware name: MSI MS-7A45/B150M MORTAR ARCTIC (MS-7A45), BIOS 1.50 04/25/2017

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