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Searched refs:MAX_PIPES (Results 1 – 25 of 48) sorted by relevance

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/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h249 struct mem_input *mis[MAX_PIPES];
250 struct hubp *hubps[MAX_PIPES];
251 struct input_pixel_processor *ipps[MAX_PIPES];
252 struct transform *transforms[MAX_PIPES];
253 struct dpp *dpps[MAX_PIPES];
254 struct output_pixel_processor *opps[MAX_PIPES];
255 struct timing_generator *timing_generators[MAX_PIPES];
256 struct stream_encoder *stream_enc[MAX_PIPES * 2];
260 struct dce_aux *engines[MAX_PIPES];
261 struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_enc_cfg.c113 for (i = 0; i < MAX_PIPES; i++) { in remove_link_enc_assignment()
237 for (i = 0; i < MAX_PIPES; i++) { in get_link_enc_used_by_link()
251 for (i = 0; i < MAX_PIPES; i++) { in clear_enc_assignments()
301 for (i = 0; i < MAX_PIPES; i++) in link_enc_cfg_link_encs_assign()
384 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
390 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
401 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_link_encs_assign()
454 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_stream_using_link_enc()
494 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_link_enc_used_by_link()
516 for (i = 0; i < MAX_PIPES; i++) { in link_enc_cfg_get_next_avail_link_enc()
[all …]
Ddc_stream.c265 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_attributes()
371 for (i = 0; i < MAX_PIPES; i++) { in program_cursor_position()
567 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_vblank_counter()
595 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_send_dp_sdp()
626 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_scanoutpos()
653 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_dmdata_status_done()
659 if (i == MAX_PIPES) in dc_stream_dmdata_status_done()
681 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_set_dynamic_metadata()
687 if (i == MAX_PIPES) in dc_stream_set_dynamic_metadata()
721 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_pipe_ctx()
Ddc.c412 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_adjust_vmin_vmax()
448 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_last_used_drr_vtotal()
478 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crtc_position()
516 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_forward_dmcu_crc_window()
523 if (i == MAX_PIPES) in dc_stream_forward_dmcu_crc_window()
550 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_stop_dmcu_crc_win_update()
557 if (i == MAX_PIPES) in dc_stream_stop_dmcu_crc_win_update()
595 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_configure_crc()
601 if (i == MAX_PIPES) in dc_stream_configure_crc()
663 for (i = 0; i < MAX_PIPES; i++) { in dc_stream_get_crc()
[all …]
Ddc_debug.c312 int h_pos[MAX_PIPES] = {0}, v_pos[MAX_PIPES] = {0}; in context_timing_trace()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dccg.h132 type OTG_ADD_PIXEL[MAX_PIPES];\
133 type OTG_DROP_PIXEL[MAX_PIPES];
168 type DTBCLK_DTO_ENABLE[MAX_PIPES];\
169 type DTBCLKDTO_ENABLE_STATUS[MAX_PIPES];\
170 type PIPE_DTO_SRC_SEL[MAX_PIPES];\
171 type DTBCLK_DTO_DIV[MAX_PIPES];\
254 uint32_t OTG_PIXEL_RATE_CNTL[MAX_PIPES];
261 uint32_t DTBCLK_DTO_MODULO[MAX_PIPES];
262 uint32_t DTBCLK_DTO_PHASE[MAX_PIPES];
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/inc/hw/
Dopp.h200 int dpp[MAX_PIPES];
201 int mpcc[MAX_PIPES];
209 bool mpcc_disconnect_pending[MAX_PIPES];
Ddccg.h69 int pipe_dppclk_khz[MAX_PIPES];
Dhw_shared.h38 #define MAX_PIPES 6 macro
Dclk_mgr_internal.h338 unsigned int cur_phyclk_req_table[MAX_PIPES * 2];
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dce/
Ddce_clock_source.h234 uint32_t PHASE[MAX_PIPES];
235 uint32_t MODULO[MAX_PIPES];
236 uint32_t PIXEL_RATE_CNTL[MAX_PIPES];
Ddmub_psr.c34 #define MAX_PIPES 6 macro
311 for (i = 0; i < MAX_PIPES; i++) { in dmub_psr_copy_settings()
Ddce_clk_mgr.c189 for (i = 0; i < MAX_PIPES; i++) { in get_max_pixel_clock_for_all_paths()
510 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
/linux-6.1.9/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_mst_types.c714 bool bpp_increased[MAX_PIPES]; in increase_dsc_bpp()
715 int initial_slack[MAX_PIPES]; in increase_dsc_bpp()
816 bool tried[MAX_PIPES]; in try_disable_dsc()
817 int kbps_increase[MAX_PIPES]; in try_disable_dsc()
887 struct dsc_mst_fairness_params params[MAX_PIPES]; in compute_mst_dsc_configs_for_link()
1015 struct amdgpu_dm_connector *stream_on_link[MAX_PIPES]; in is_dsc_need_re_compute()
1029 for (i = 0; i < MAX_PIPES; i++) in is_dsc_need_re_compute()
1112 bool computed_streams[MAX_PIPES]; in compute_mst_dsc_configs_for_state()
1173 bool computed_streams[MAX_PIPES]; in pre_compute_mst_dsc_configs_for_state()
Damdgpu_dm_debugfs.c1370 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_read()
1476 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_clock_en_write()
1561 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_read()
1665 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_width_write()
1750 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_read()
1854 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_slice_height_write()
1935 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_read()
2036 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_bits_per_pixel_write()
2115 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_width_read()
2176 for (i = 0; i < MAX_PIPES; i++) { in dp_dsc_pic_height_read()
[all …]
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_resource_helpers.c285 uint8_t pipe_plane_count, stream_segments, plane_segments, pipe_segments[MAX_PIPES] = {0}; in dcn32_determine_det_override()
286 uint8_t pipe_counted[MAX_PIPES] = {0}; in dcn32_determine_det_override()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
Ddce110_clk_mgr.c134 for (k = 0; k < MAX_PIPES; k++) in dce110_fill_display_configs()
/linux-6.1.9/drivers/net/ipa/
Dipa_reg.h305 MAX_PIPES, enumerator
/linux-6.1.9/drivers/net/ipa/reg/
Dipa_reg-v3.5.1.c144 [MAX_PIPES] = GENMASK(3, 0),
Dipa_reg-v4.2.c175 [MAX_PIPES] = GENMASK(3, 0),
Dipa_reg-v4.11.c172 [MAX_PIPES] = GENMASK(4, 0),
Dipa_reg-v4.5.c165 [MAX_PIPES] = GENMASK(3, 0),
Dipa_reg-v4.9.c171 [MAX_PIPES] = GENMASK(3, 0),
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c170 for (i = 0; i < MAX_PIPES; i++) { in dce_get_max_pixel_clock_for_all_paths()
/linux-6.1.9/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_hwseq.c187 int opp_inst[MAX_PIPES] = {0}; in dcn314_update_odm()

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