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Searched refs:HDP_HWIP (Results 1 – 8 of 8) sorted by relevance

/linux-6.1.9/drivers/gpu/drm/amd/amdgpu/
Dhdp_v4_0.c52 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0)) in hdp_v4_0_invalidate_hdp()
82 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
94 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
95 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
96 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
97 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
139 switch (adev->ip_versions[HDP_HWIP][0]) { in hdp_v4_0_init_registers()
149 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0)) in hdp_v4_0_init_registers()
Ddimgrey_cavefish_reg_init.c36 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
Daldebaran_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in aldebaran_reg_base_init()
Darct_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in arct_reg_base_init()
Damdgpu_discovery.c173 [HDP_HWIP] = HDP_HWID,
1979 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2001 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2025 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2041 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2062 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2086 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); in amdgpu_discovery_set_ip_blocks()
2114 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
2269 switch (adev->ip_versions[HDP_HWIP][0]) { in amdgpu_discovery_set_ip_blocks()
Dvega10_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega10_reg_base_init()
Dvega20_reg_init.c35 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i])); in vega20_reg_base_init()
Damdgpu.h643 HDP_HWIP, enumerator