Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (Results 1 – 1 of 1) sorted by relevance
63 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0) macro150 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ; in exynos4x12_rate_to_clk()