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Searched refs:CP0 (Results 1 – 14 of 14) sorted by relevance

/linux-6.1.9/arch/arm64/boot/dts/marvell/
Dcn9130-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
Dcn9132-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
Dcn9132-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
Dcn9131-db.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
Dcn9130-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
Dcn9131-db-B.dts15 * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated
Darmada-8040-db.dts104 /* CON6 on CP0 expansion */
111 /* CON5 on CP0 expansion */
142 /* CON4 on CP0 expansion */
156 /* CON9 on CP0 expansion */
176 /* CON10 on CP0 expansion */
Darmada-8040-clearfog-gt-8k.dts271 * [35-38] CP0 I2C1 and I2C0
441 * [29] CP0 10G SFP TX Disable
/linux-6.1.9/arch/arm/kernel/
Diwmmxt.S76 @ CP0 and CP1 accessible?
80 @ enable access to CP0 and CP1
210 @ enable access to CP0 and CP1
224 @ disable access to CP0 and CP1
325 @ CP0 and CP1 accessible?
/linux-6.1.9/arch/arm/boot/dts/
Daspeed-bmc-opp-mihawk.dts655 /* CP0 VDD & VCS : IR35221 */
656 /* CP0 VDN : IR35221 */
657 /* CP0 VIO : IR38064 */
658 /* CP0 VDDR : PXM1330 */
675 /* CP0 VDD & VCS : IR35221 */
676 /* CP0 VDN : IR35221 */
677 /* CP0 VIO : IR38064 */
678 /* CP0 VDDR : PXM1330 */
Daspeed-bmc-opp-mowgli.dts524 /* CP0 VDD & VCS : IR35221 */
525 /* CP0 VDN & VIO : IR35221 */
526 /* CP0 VDDR : IR35221 */
/linux-6.1.9/drivers/gpu/drm/radeon/
Dcikd.h850 #define CP0 (1 << 0) macro
Dcik.c3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit()
/linux-6.1.9/Documentation/virt/kvm/
Dapi.rst2680 MIPS CP0 registers (see KVM_REG_MIPS_CP0_* above) have the following id bit