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Searched refs:CLK_SMMU_MFCL (Results 1 – 9 of 9) sorted by relevance

/linux-6.1.9/include/dt-bindings/clock/
Dexynos5250.h71 #define CLK_SMMU_MFCL 267 macro
Dexynos5420.h137 #define CLK_SMMU_MFCL 402 macro
Dexynos4.h112 #define CLK_SMMU_MFCL 274 macro
/linux-6.1.9/drivers/clk/samsung/
Dclk-exynos5250.c544 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "mout_aclk333_sub", GATE_IP_MFC, 2, 0,
Dclk-exynos4.c824 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "aclk100", GATE_IP_MFC, 1,
Dclk-exynos5420.c1280 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
/linux-6.1.9/arch/arm/boot/dts/
Dexynos4.dtsi887 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
Dexynos5250.dtsi878 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
Dexynos5420.dtsi1032 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;