Searched refs:CLK_FIN_PLL (Results 1 – 20 of 20) sorted by relevance
| /linux-6.1.9/Documentation/devicetree/bindings/timer/ |
| D | samsung,exynos4210-mct.yaml | 165 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
185 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
206 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
226 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| /linux-6.1.9/include/dt-bindings/clock/ |
| D | exynos5410.h | 13 #define CLK_FIN_PLL 1 macro
|
| D | exynos5250.h | 13 #define CLK_FIN_PLL 1 macro
|
| D | exynos5420.h | 13 #define CLK_FIN_PLL 1 macro
|
| D | exynos4.h | 15 #define CLK_FIN_PLL 3 macro
|
| D | exynos3250.h | 26 #define CLK_FIN_PLL 2 macro
|
| /linux-6.1.9/Documentation/devicetree/bindings/soc/samsung/ |
| D | exynos-pmu.yaml | 132 clocks = <&clock CLK_FIN_PLL>;
|
| /linux-6.1.9/arch/arm/boot/dts/ |
| D | exynos3250.dtsi | 179 clocks = <&cmu CLK_FIN_PLL>;
230 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
231 <&cmu CLK_FIN_PLL>;
283 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
|
| D | exynos5250.dtsi | 241 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
251 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
296 clocks = <&clock CLK_FIN_PLL>;
658 clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
689 clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
|
| D | exynos5420.dtsi | 187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
828 clocks = <&clock CLK_FIN_PLL>;
1294 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| D | exynos4210.dtsi | 125 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| D | exynos5250-snow-common.dtsi | 672 assigned-clock-parents = <&clock CLK_FIN_PLL>;
|
| D | exynos4412.dtsi | 268 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
| D | exynos4.dtsi | 70 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
|
| D | exynos5420-peach-pit.dts | 942 assigned-clock-parents = <&clock CLK_FIN_PLL>;
|
| D | exynos5800-peach-pi.dts | 924 assigned-clock-parents = <&clock CLK_FIN_PLL>;
|
| /linux-6.1.9/drivers/clk/samsung/ |
| D | clk-exynos5250.c | 225 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
809 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5250_clk_init()
|
| D | clk-exynos4.c | 1054 fclk.id = CLK_FIN_PLL; in exynos4_clk_register_finpll()
1267 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
1281 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24000000) { in exynos4_clk_init()
|
| D | clk-exynos5420.c | 445 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
1597 if (clk_hw_get_rate(hws[CLK_FIN_PLL]) == 24 * MHZ) { in exynos5x_clk_init()
|
| D | clk-exynos3250.c | 234 FFACTOR(CLK_FIN_PLL, "fin_pll", "xusbxti", 1, 1, 0),
|