| /linux-6.1.9/arch/arm/boot/dts/ |
| D | vexpress-v2p-ca15_a7.dts | 257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
338 /* A15 CPU core voltage */
341 regulator-name = "A15 Vcore";
345 label = "A15 Vcore";
360 /* Total current for the two A15 cores */
363 label = "A15 Icore";
381 /* Total power for the two A15 cores */
384 label = "A15 Pcore";
395 /* Total energy for the two A15 cores */
[all …]
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| D | exynos5420-cpus.dtsi | 9 * boards: CPU[0123] being the A15.
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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| D | exynos5422-odroidxu3.dts | 27 /* A15 cluster: VDD_ARM */
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| D | xenvm-4.2.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
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| D | exynos5422-odroidxu3-lite.dts | 39 * than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
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| D | exynos5422-cpus.dtsi | 13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
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| D | am335x-boneblue.dts | 124 …AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0…
459 "WIFI_LED", /* A15 */
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| D | vexpress-v2p-ca15-tc1.dts | 6 * Cortex-A15 MPCore (V2P-CA15)
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| /linux-6.1.9/arch/arm/include/debug/ |
| D | exynos.S | 23 teq \tmp, #0xf0 @@ A15
27 teq \tmp, #0x100 @@ A15 + A7 but boot to A7
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| /linux-6.1.9/Documentation/devicetree/bindings/arm/ |
| D | calxeda.yaml | 13 or Cortex-A15 based ECX-2000 SOCs
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| D | arm,vexpress-juno.yaml | 57 - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
64 A15 CPU cores in a test chip on the core tile. This is the first test
70 - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
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| D | l2c2x0.yaml | 22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
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| /linux-6.1.9/Documentation/devicetree/bindings/hwmon/ |
| D | vexpress.txt | 22 label = "A15 Jcore";
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| /linux-6.1.9/Documentation/devicetree/bindings/timer/ |
| D | nxp,sysctr-timer.yaml | 14 which provides a shared time base to Cortex A15, A7, A53, A73,
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| /linux-6.1.9/arch/arm/mach-hisi/ |
| D | Kconfig | 37 bool "Hisilicon HiP04 Cortex A15 family"
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| /linux-6.1.9/Documentation/arm/keystone/ |
| D | overview.rst | 7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
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| /linux-6.1.9/arch/arm/mach-exynos/ |
| D | Kconfig | 67 Samsung Exynos5 (Cortex-A15/A7) SoC based systems
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| /linux-6.1.9/Documentation/arm/ |
| D | sunxi.rst | 123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
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| /linux-6.1.9/drivers/pinctrl/aspeed/ |
| D | pinctrl-aspeed-g5.c | 584 #define A15 71 macro
592 SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1);
593 SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC);
594 PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO);
596 FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
597 FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
598 FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
599 FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
1908 ASPEED_PINCTRL_PIN(A15),
2527 ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24),
[all …]
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| D | pinctrl-aspeed-g6.c | 574 #define A15 71 macro
575 SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7));
576 SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7));
577 PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI);
578 FUNC_GROUP_DECL(BMCINT, A15);
579 FUNC_GROUP_DECL(SIOSCI, A15);
1641 ASPEED_PINCTRL_PIN(A15),
2412 ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7),
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| D | pinctrl-aspeed-g4.c | 334 #define A15 35 macro
335 SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
338 SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE);
339 PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT);
341 FUNC_GROUP_DECL(NRI3, A15);
342 FUNC_GROUP_DECL(GPIE2, B15, A15);
1914 ASPEED_PINCTRL_PIN(A15),
2539 ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25),
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| /linux-6.1.9/drivers/soc/tegra/ |
| D | Kconfig | 75 Tegra124's "4+1" Cortex-A15 CPU complex.
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| /linux-6.1.9/arch/arm/crypto/ |
| D | Kconfig | 181 Bit sliced AES gives around 45% speedup on Cortex-A15 for CTR mode
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| /linux-6.1.9/arch/arm/kernel/ |
| D | entry-header.S | 350 @ We must avoid clrex due to Cortex-A15 erratum #830321
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| /linux-6.1.9/arch/arm/mm/ |
| D | proc-v7.S | 517 ldr r10, =0x00000c0f @ Cortex-A15 primary part number
618 @ Cortex-A15 - needs iciallu switch_mm for hardening
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