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/linux-5.19.10/arch/arm/boot/dts/
Dimx6qdl-skov-revc-lt2.dtsi69 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
70 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
71 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
72 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
73 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
74 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
75 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
76 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
77 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
78 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6dl-skov-revc-lt6.dts76 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
77 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
80 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
81 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
82 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
83 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
84 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
85 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-phytec-mira-peb-av-02.dtsi77 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
81 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
82 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
83 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
84 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
85 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
86 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
87 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
Dimx6q-skov-revc-lt6.dts98 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
99 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
100 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
101 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
102 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
103 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
104 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
105 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
106 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
107 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dam335x-pocketbeagle.dts221 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
222 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
230 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
231 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
239 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
240 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
248 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
249 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
257 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
258 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
[all …]
Dimx6qdl-aristainetos.dtsi296 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10
323 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
324 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
325 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
326 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
328 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
329 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
330 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
331 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
332 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
Dimx6q-kp.dtsi287 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
288 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
289 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
290 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
291 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
292 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
293 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
294 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
295 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
296 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-tx6.dtsi378 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
379 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
380 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
381 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
383 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
384 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
385 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
386 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
387 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
388 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
Dimx6ul-tx6ul.dtsi597 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
598 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
599 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
600 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
602 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
603 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
604 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
605 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
606 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
607 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
[all …]
Dimx6ul-tx6ul-mainboard.dts203 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
204 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
205 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
206 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
207 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
208 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
209 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
210 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
211 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
212 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
[all …]
Dimx6dl-mamoj.dts401 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
402 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
403 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */
404 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */
405 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */
406 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
407 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
408 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
409 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
410 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
Dimx6qdl-pico.dtsi477 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
478 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
479 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
480 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
481 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
482 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
483 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
484 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
485 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
486 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
Dimx6qdl-nitrogen6x.dtsi460 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
461 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
462 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
463 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
464 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
465 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
466 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
467 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
468 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
469 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6dl-yapp4-common.dtsi421 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
422 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
423 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
424 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
425 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
426 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
427 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
428 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
429 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
430 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
Dimx6qdl-emcon.dtsi577 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
578 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
579 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
580 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
581 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
582 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
583 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
584 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
585 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
586 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-nitrogen6_som2.dtsi442 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
443 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
444 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
445 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
446 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
447 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
448 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
449 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
450 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
451 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-nitrogen6_max.dtsi539 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
540 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
541 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
542 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
543 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
544 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
545 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
546 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
547 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
548 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
Dimx6qdl-sabrelite.dtsi554 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
555 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
556 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
557 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
558 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
559 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
560 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
561 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
562 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
563 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
/linux-5.19.10/fs/unicode/
Dutf8data.c_shipped96 0xe1,0x8d,0xa9,0x10,0x08,0x01,0xff,0xe8,0xb1,0x88,0x00,0x01,0xff,0xe6,0x9b,0xb4,
98 0xab,0x10,0x08,0x01,0xff,0xe9,0xb9,0xbf,0x00,0x01,0xff,0xe8,0xab,0x96,0x00,0xe3,
99 0x09,0xac,0xe2,0xe8,0xab,0xe1,0xd7,0xab,0x10,0x08,0x01,0xff,0xe7,0xb8,0xb7,0x00,
109 0x4e,0xe3,0xe2,0x2d,0xe3,0xe1,0x1b,0xe3,0x10,0x08,0x05,0xff,0xe4,0xb8,0xbd,0x00,
111 0xe2,0x0e,0xe5,0xe1,0xfd,0xe4,0x10,0x08,0x05,0xff,0xe5,0x92,0xa2,0x00,0x05,0xff,
112 0xe5,0x93,0xb6,0x00,0xd4,0x34,0xd3,0x18,0xe2,0xf7,0xe5,0xe1,0xe6,0xe5,0x10,0x09,
114 0xe6,0x91,0x11,0x10,0x09,0x05,0xff,0xf0,0xa1,0x8d,0xaa,0x00,0x05,0xff,0xe5,0xac,
116 0x10,0x08,0x05,0xff,0xe5,0xaf,0xb3,0x00,0x05,0xff,0xf0,0xa1,0xac,0x98,0x00,0xe1,
117 0x38,0xe6,0x10,0x08,0x05,0xff,0xe5,0xbc,0xb3,0x00,0x05,0xff,0xe5,0xb0,0xa2,0x00,
119 0xea,0xe1,0x93,0xea,0x10,0x08,0x05,0xff,0xe6,0xb4,0xbe,0x00,0x05,0xff,0xe6,0xb5,
[all …]
/linux-5.19.10/drivers/scsi/aic7xxx/
Daic79xx_reg_print.c_shipped16 { "PCIINT", 0x10, 0x10 },
47 { "SEQ_SWTMRTO", 0x10, 0x10 }
62 { "AUTOCLRCMDINT", 0x10, 0x10 },
101 { "MREQPEND", 0x10, 0x10 },
129 { "FORCEBUSFREE", 0x10, 0x10 },
146 { "ENRSELI", 0x10, 0x10 },
162 { "FIFO0FREE", 0x10, 0x10 },
187 { "ATNI", 0x10, 0x10 },
207 { "COMMAND_PHASE", 0x10, 0x10 },
242 { "ENSELINGO", 0x10, 0x10 },
[all …]
Daic7xxx_reg_print.c_shipped16 { "ENRSELI", 0x10, 0x10 },
33 { "CLRSTCNT", 0x10, 0x10 },
51 { "ATNI", 0x10, 0x10 },
74 { "SINGLE_EDGE", 0x10, 0x10 },
95 { "SELINGO", 0x10, 0x10 },
113 { "PHASEMIS", 0x10, 0x10 },
131 { "EXP_ACTIVE", 0x10, 0x10 },
163 { "ENSELINGO", 0x10, 0x10 },
172 0x10, regvalue, cur_col, wrap));
180 { "ENPHASEMIS", 0x10, 0x10 },
[all …]
Daic79xx_reg.h_shipped375 #define PCIINT 0x10
392 #define STATUS_OVERRUN 0x10
414 #define CLRPCIINT 0x10
424 #define CLRDPARERR 0x10
433 #define DPARERR 0x10
441 #define SWINT 0x10
457 #define SEQ_SWTMRTO 0x10
464 #define CLRSEQ_SWTMRTO 0x10
472 #define SNSCB_QOFF 0x10
482 #define HS_MAILBOX_ACT 0x10
[all …]
Daic7xxx_reg.h_shipped75 ahc_print_register(NULL, 0, "SIMODE0", 0x10, regvalue, cur_col, wrap)
199 #define CLRSTCNT 0x10
216 #define ATNO 0x10
225 #define ATNI 0x10
237 #define SINGLE_EDGE 0x10
252 #define BUSFREEREV 0x10
265 #define CLRSELINGO 0x10
274 #define SELINGO 0x10
294 #define PHASEMIS 0x10
304 #define EXP_ACTIVE 0x10
[all …]
/linux-5.19.10/arch/arm64/mm/
Dproc.S86 mrs x10, oslsr_el1
94 stp x10, x11, [x0, #64]
114 ldp x9, x10, [x0, #48]
143 msr mdscr_el1, x10
238 pud .req x10
431 mrs x10, ID_AA64PFR1_EL1
432 ubfx x10, x10, #ID_AA64PFR1_MTE_SHIFT, #4
433 cmp x10, #ID_AA64PFR1_MTE
437 mov x10, #MAIR_ATTR_NORMAL_TAGGED
438 bfi mair, x10, #(8 * MT_NORMAL_TAGGED), #8
[all …]
/linux-5.19.10/Documentation/devicetree/bindings/
Dresource-names.txt31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;

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