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Searched refs:spx5_rd (Results 1 – 10 of 10) sorted by relevance

/linux-5.19.10/drivers/net/ethernet/microchip/sparx5/
Dsparx5_packet.c68 ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); in sparx5_xtr_grp()
95 u32 val = spx5_rd(sparx5, QS_XTR_RD(grp)); in sparx5_xtr_grp()
127 *rxbuf = spx5_rd(sparx5, QS_XTR_RD(grp)); in sparx5_xtr_grp()
171 val = spx5_rd(sparx5, QS_INJ_STATUS); in sparx5_inject()
211 val = spx5_rd(sparx5, QS_INJ_STATUS); in sparx5_inject()
279 val = spx5_rd(port->sparx5, QS_INJ_STATUS); in sparx5_injection_timeout()
342 while (spx5_rd(s5, QS_XTR_DATA_PRESENT) & BIT(XTR_QUEUE) && poll-- > 0) in sparx5_xtr_handler()
Dsparx5_ptp.c292 ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); in sparx5_get_hwtimestamp()
293 curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); in sparx5_get_hwtimestamp()
318 val = spx5_rd(sparx5, REW_PTP_TWOSTEP_CTRL); in sparx5_ptp_irq_handler()
336 delay = spx5_rd(sparx5, REW_PTP_TWOSTEP_STAMP); in sparx5_ptp_irq_handler()
346 val = spx5_rd(sparx5, REW_PTP_TWOSTEP_CTRL); in sparx5_ptp_irq_handler()
353 id = spx5_rd(sparx5, REW_PTP_TWOSTEP_STAMP); in sparx5_ptp_irq_handler()
355 id |= spx5_rd(sparx5, REW_PTP_TWOSTEP_STAMP_SUBNS); in sparx5_ptp_irq_handler()
498 s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); in sparx5_ptp_gettime64()
500 s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); in sparx5_ptp_gettime64()
501 ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); in sparx5_ptp_gettime64()
Dsparx5_vlan.c143 portmask[0] = spx5_rd(spx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_read_mask()
144 portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_read_mask()
145 portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_read_mask()
Dsparx5_mactable.c46 return spx5_rd(sparx5, LRN_COMMON_ACCESS_CTRL); in sparx5_mact_get_status()
141 cfg2 = spx5_rd(sparx5, LRN_MAC_ACCESS_CFG_2); in sparx5_mact_get()
143 mach = spx5_rd(sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_get()
144 macl = spx5_rd(sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_get()
206 cfg2 = spx5_rd(sparx5, LRN_MAC_ACCESS_CFG_2); in sparx5_mact_find()
Dsparx5_fdma.c467 db = spx5_rd(sparx5, FDMA_INTR_DB); in sparx5_fdma_handler()
468 err = spx5_rd(sparx5, FDMA_INTR_ERR); in sparx5_fdma_handler()
476 u32 err_type = spx5_rd(sparx5, FDMA_ERRORS); in sparx5_fdma_handler()
582 return spx5_rd(sparx5, FDMA_PORT_CTRL(0)); in sparx5_fdma_port_ctrl()
Dsparx5_port.c86 value = spx5_rd(sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
92 value = spx5_rd(sparx5, DEV2G5_PCS1G_LINK_STATUS(portno)); in sparx5_get_dev2g5_status()
104 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_STATUS(portno)); in sparx5_get_dev2g5_status()
112 value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno)); in sparx5_get_dev2g5_status()
290 value = spx5_rd(sparx5, in sparx5_port_flush_poll()
Dsparx5_ethtool.c214 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
218 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
222 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
224 spx5_rd(sparx5, XQS_CNT(32))); in sparx5_get_queue_sys_stats()
226 spx5_rd(sparx5, XQS_CNT(272))); in sparx5_get_queue_sys_stats()
235 spx5_rd(sparx5, ANA_AC_PORT_STAT_LSB_CNT(portno, in sparx5_get_ana_ac_stats_stats()
Dsparx5_calendar.c239 value = spx5_rd(sparx5, QSYS_CAL_CTRL); in sparx5_config_auto_calendar()
555 len = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(spx5_rd(sparx5, in sparx5_dsm_calendar_update()
Dsparx5_main.c395 value = spx5_rd(sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
830 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); in mchp_sparx5_probe()
Dsparx5_main.h452 static inline u32 spx5_rd(struct sparx5 *sparx5, int id, int tinst, int tcnt, in spx5_rd() function