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Searched refs:rFPGA0_XCD_RFInterfaceSW (Results 1 – 9 of 9) sorted by relevance

/linux-5.19.10/drivers/staging/rtl8192u/
Dr819xU_phyreg.h29 #define rFPGA0_XCD_RFInterfaceSW 0x874 macro
Dr819xU_phy.c553 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl8192_InitBBRFRegDef()
555 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; in rtl8192_InitBBRFRegDef()
/linux-5.19.10/drivers/staging/r8188eu/hal/
DHalPhyRf_8188e.c656 rFPGA0_XCD_RFInterfaceSW, rConfig_AntA, rConfig_AntB, in phy_IQCalibrate_8188E()
684 rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); in phy_IQCalibrate_8188E()
/linux-5.19.10/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h74 #define rFPGA0_XCD_RFInterfaceSW 0x874 macro
Dr8192E_phy.c384 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()
385 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()
/linux-5.19.10/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h116 #define rFPGA0_XCD_RFInterfaceSW 0x874 macro
/linux-5.19.10/drivers/staging/r8188eu/include/
DHal8188EPhyReg.h82 #define rFPGA0_XCD_RFInterfaceSW 0x874 macro
/linux-5.19.10/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h128 #define rFPGA0_XCD_RFInterfaceSW 0x874 macro
/linux-5.19.10/drivers/staging/rtl8723bs/hal/
DHalPhyRf_8723B.c1358 rFPGA0_XCD_RFInterfaceSW, in phy_IQCalibrate_8723B()
1397 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); in phy_IQCalibrate_8723B()