Searched refs:mmSDMA0_PHASE2_QUANTUM (Results 1 – 8 of 8) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_0_offset.h | 172 #define mmSDMA0_PHASE2_QUANTUM 0x004f macro
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| D | sdma0_4_2_2_offset.h | 172 #define mmSDMA0_PHASE2_QUANTUM … macro
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| D | sdma0_4_2_offset.h | 172 #define mmSDMA0_PHASE2_QUANTUM … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v5_2.c | 560 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_2_ctx_switch_enable()
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| D | sdma_v5_0.c | 663 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM), in sdma_v5_0_ctx_switch_enable()
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| D | sdma_v4_0.c | 1102 WREG32_SDMA(i, mmSDMA0_PHASE2_QUANTUM, phase_quantum); in sdma_v4_0_ctx_switch_enable()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 147 #define mmSDMA0_PHASE2_QUANTUM … macro
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| D | gc_10_3_0_offset.h | 142 #define mmSDMA0_PHASE2_QUANTUM … macro
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