Searched refs:mmSDMA0_GFX_RB_WPTR (Results 1 – 16 of 16) sorted by relevance
| /linux-5.19.10/drivers/gpu/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 210 u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v2_4_ring_get_wptr()
226 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); in sdma_v2_4_ring_set_wptr()
450 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
466 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); in sdma_v2_4_gfx_resume()
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| D | cik_sdma.c | 183 return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2; in cik_sdma_ring_get_wptr()
197 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
488 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2); in cik_sdma_gfx_resume()
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| D | sdma_v5_2.c | 276 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_2_ring_get_wptr()
317 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_2_ring_set_wptr()
641 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_2_gfx_resume()
675 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); in sdma_v5_2_gfx_resume()
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| D | sdma_v5_0.c | 375 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr()
416 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_ring_set_wptr()
740 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); in sdma_v5_0_gfx_resume()
776 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), in sdma_v5_0_gfx_resume()
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| D | sdma_v3_0.c | 372 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; in sdma_v3_0_ring_get_wptr()
399 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2); in sdma_v3_0_ring_set_wptr()
725 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
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| D | sdma_v4_0.c | 750 wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); in sdma_v4_0_ring_get_wptr()
793 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR, in sdma_v4_0_ring_set_wptr()
1188 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR, 0); in sdma_v4_0_gfx_resume()
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| D | sdma0_4_1_offset.h | 214 #define mmSDMA0_GFX_RB_WPTR … macro
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| D | sdma0_4_0_offset.h | 218 #define mmSDMA0_GFX_RB_WPTR 0x0085 macro
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| D | sdma0_4_2_2_offset.h | 218 #define mmSDMA0_GFX_RB_WPTR … macro
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| D | sdma0_4_2_offset.h | 214 #define mmSDMA0_GFX_RB_WPTR … macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/ |
| D | oss_2_4_d.h | 191 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| D | oss_3_0_1_d.h | 218 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| D | oss_2_0_d.h | 250 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| D | oss_3_0_d.h | 343 #define mmSDMA0_GFX_RB_WPTR 0x3484 macro
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| /linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| D | gc_10_1_0_offset.h | 212 #define mmSDMA0_GFX_RB_WPTR … macro
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| D | gc_10_3_0_offset.h | 198 #define mmSDMA0_GFX_RB_WPTR … macro
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