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Searched refs:mmSDMA0_CLK_CTRL (Results 1 – 17 of 17) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/amdgpu/
Dsdma_v3_0.c83 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
96 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
114 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
121 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
135 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
149 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
164 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
178 mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
1451 temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
1461 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data); in sdma_v3_0_update_sdma_medium_grain_clock_gating()
[all …]
Dmxgpu_vi.c94 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
225 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
246 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
Dcik_sdma.c892 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
893 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
895 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
898 WREG32(mmSDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
900 orig = data = RREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
903 WREG32(mmSDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
Dsdma_v4_0.c91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
158 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
284 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
2279 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); in sdma_v4_0_update_medium_grain_clock_gating()
2289 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); in sdma_v4_0_update_medium_grain_clock_gating()
2293 def = data = RREG32_SDMA(i, mmSDMA0_CLK_CTRL); in sdma_v4_0_update_medium_grain_clock_gating()
2303 WREG32_SDMA(i, mmSDMA0_CLK_CTRL, data); in sdma_v4_0_update_medium_grain_clock_gating()
2378 data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_CLK_CTRL)); in sdma_v4_0_get_clockgating_state()
Dsdma_v5_2.c1660 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_2_update_medium_grain_clock_gating()
1668 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_2_update_medium_grain_clock_gating()
1671 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_2_update_medium_grain_clock_gating()
1679 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_2_update_medium_grain_clock_gating()
1756 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); in sdma_v5_2_get_clockgating_state()
Dsdma_v5_0.c1667 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_0_update_medium_grain_clock_gating()
1677 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_0_update_medium_grain_clock_gating()
1680 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL)); in sdma_v5_0_update_medium_grain_clock_gating()
1690 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data); in sdma_v5_0_update_medium_grain_clock_gating()
1759 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL)); in sdma_v5_0_get_clockgating_state()
Dsdma_v2_4.c69 mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
76 mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h66 #define mmSDMA0_CLK_CTRL … macro
Dsdma0_4_0_offset.h68 #define mmSDMA0_CLK_CTRL 0x001b macro
Dsdma0_4_2_2_offset.h68 #define mmSDMA0_CLK_CTRL … macro
Dsdma0_4_2_offset.h68 #define mmSDMA0_CLK_CTRL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h160 #define mmSDMA0_CLK_CTRL 0x3403 macro
Doss_3_0_1_d.h157 #define mmSDMA0_CLK_CTRL 0x3403 macro
Doss_2_0_d.h222 #define mmSDMA0_CLK_CTRL 0x3403 macro
Doss_3_0_d.h294 #define mmSDMA0_CLK_CTRL 0x3403 macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h43 #define mmSDMA0_CLK_CTRL … macro
Dgc_10_3_0_offset.h48 #define mmSDMA0_CLK_CTRL … macro