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Searched refs:mmDP0_DP_VID_INTERRUPT_CNTL (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h3161 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF macro
Ddce_8_0_d.h3860 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x1ccf macro
Ddce_10_0_d.h4492 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae macro
Ddce_11_0_d.h4468 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae macro
Ddce_11_2_d.h5700 #define mmDP0_DP_VID_INTERRUPT_CNTL 0x4aae macro
Ddce_12_0_offset.h10222 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_2_0_3_offset.h5490 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_3_0_3_offset.h4976 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_3_0_1_offset.h7946 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_1_0_offset.h8375 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_2_1_0_offset.h9879 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_3_0_2_offset.h9558 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_2_0_0_offset.h10972 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro
Ddcn_3_0_0_offset.h10693 #define mmDP0_DP_VID_INTERRUPT_CNTL … macro