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Searched refs:ixAZALIA_INPUT_CRC0_CHANNEL1 (Results 1 – 14 of 14) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_10_0_d.h6696 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 macro
Ddce_11_0_d.h6858 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 macro
Ddce_11_2_d.h8203 #define ixAZALIA_INPUT_CRC0_CHANNEL1 0x1 macro
Ddce_12_0_offset.h18085 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
/linux-5.19.10/drivers/gpu/drm/amd/include/asic_reg/dcn/
Ddcn_3_0_3_offset.h7368 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_3_0_1_offset.h12211 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_1_0_offset.h13055 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_2_1_0_offset.h12815 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_3_1_2_offset.h14025 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_3_1_5_offset.h14131 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_3_0_2_offset.h15100 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_3_1_6_offset.h14622 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_2_0_0_offset.h16479 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro
Ddcn_3_0_0_offset.h16822 #define ixAZALIA_INPUT_CRC0_CHANNEL1 … macro