Searched refs:h264_dec (Results 1 – 4 of 4) sorted by relevance
204 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; in assemble_scaling_list()210 struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; in assemble_scaling_list()234 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; in prepare_table()237 struct hantro_h264_dec_priv_tbl *tbl = ctx->h264_dec.priv.cpu; in prepare_table()238 const struct v4l2_h264_dpb_entry *dpb = ctx->h264_dec.dpb; in prepare_table()275 ctx->h264_dec.dpb_valid = dpb_valid; in prepare_table()276 ctx->h264_dec.dpb_longterm = dpb_longterm; in prepare_table()280 tbl->poc[32] = ctx->h264_dec.cur_poc; in prepare_table()303 dec_param = ctx->h264_dec.ctrls.decode; in update_dpb()306 for (i = 0; i < ARRAY_SIZE(ctx->h264_dec.dpb); i++) in update_dpb()[all …]
24 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; in set_params()135 vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_valid, G1_REG_VALID_REF); in set_ref()136 vdpu_write_relaxed(vpu, ctx->h264_dec.dpb_longterm, G1_REG_LT_REF); in set_ref()150 b0_reflist = ctx->h264_dec.reflists.b0; in set_ref()151 b1_reflist = ctx->h264_dec.reflists.b1; in set_ref()152 p_reflist = ctx->h264_dec.reflists.p; in set_ref()207 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; in set_buffers()247 vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, G1_REG_ADDR_QTABLE); in set_buffers()
195 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; in set_params()306 b0_reflist = ctx->h264_dec.reflists.b0; in set_ref()307 b1_reflist = ctx->h264_dec.reflists.b1; in set_ref()308 p_reflist = ctx->h264_dec.reflists.p; in set_ref()408 reg = VDPU_REG_REFER_LTERM_E(ctx->h264_dec.dpb_longterm); in set_ref()411 reg = VDPU_REG_REFER_VALID_E(ctx->h264_dec.dpb_valid); in set_ref()424 const struct hantro_h264_dec_ctrls *ctrls = &ctx->h264_dec.ctrls; in set_buffers()464 vdpu_write_relaxed(vpu, ctx->h264_dec.priv.dma, VDPU_REG_QTABLE_BASE); in set_buffers()
261 struct hantro_h264_dec_hw_ctx h264_dec; member