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Searched refs:TLBTEMP_BASE_2 (Results 1 – 3 of 3) sorted by relevance

/linux-5.19.10/Documentation/xtensa/
Dmmu.rst89 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
132 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
176 | Cache aliasing | TLBTEMP_BASE_2 DCACHE_WAY_SIZE
/linux-5.19.10/arch/xtensa/mm/
Dcache.c107 void *src_vaddr = coherent_kvaddr(src, TLBTEMP_BASE_2, vaddr, in copy_user_highpage()
/linux-5.19.10/arch/xtensa/include/asm/
Dpgtable.h72 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) macro