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Searched refs:PUNIT_REG_DSPSSPM (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/drivers/gpu/drm/i915/
Dvlv_sideband_reg.h37 #define PUNIT_REG_DSPSSPM 0x36 macro
Dintel_pm.c365 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_memory_pm5()
370 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_memory_pm5()
6993 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_wm_get_hw_state()
/linux-5.19.10/drivers/gpu/drm/i915/display/
Dintel_display_power_well.c1644 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1657 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1678 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1683 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_pipe_power_well()
1686 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl); in chv_set_pipe_power_well()
1692 vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM)); in chv_set_pipe_power_well()
Dintel_cdclk.c529 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_get_cdclk()
612 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in vlv_set_cdclk()
615 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in vlv_set_cdclk()
616 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
696 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM); in chv_set_cdclk()
699 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val); in chv_set_cdclk()
700 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()