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Searched refs:IXGB_WRITE_REG (Results 1 – 4 of 4) sorted by relevance

/linux-5.19.10/drivers/net/ethernet/intel/ixgb/
Dixgb_ee.c34 IXGB_WRITE_REG(hw, EECD, *eecd_reg); in ixgb_raise_clock()
53 IXGB_WRITE_REG(hw, EECD, *eecd_reg); in ixgb_lower_clock()
91 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_shift_out_bits()
105 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_shift_out_bits()
165 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_setup_eeprom()
169 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_setup_eeprom()
186 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_standby_eeprom()
192 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_standby_eeprom()
198 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_standby_eeprom()
204 IXGB_WRITE_REG(hw, EECD, eecd_reg); in ixgb_standby_eeprom()
[all …]
Dixgb_hw.c64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
82 IXGB_WRITE_REG(hw, CTRL1, ctrl_reg); in ixgb_mac_reset()
119 IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF); in ixgb_adapter_stop()
125 IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN); in ixgb_adapter_stop()
126 IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN); in ixgb_adapter_stop()
141 IXGB_WRITE_REG(hw, IMC, 0xffffffff); in ixgb_adapter_stop()
294 IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST); in ixgb_init_hw()
667 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_setup_fc()
670 IXGB_WRITE_REG(hw, PAP, pap_reg); in ixgb_setup_fc()
679 IXGB_WRITE_REG(hw, FCRTL, 0); in ixgb_setup_fc()
[all …]
Dixgb_main.c150 IXGB_WRITE_REG(&adapter->hw, IMC, ~0); in ixgb_irq_disable()
167 IXGB_WRITE_REG(&adapter->hw, IMS, val); in ixgb_irq_enable()
192 IXGB_WRITE_REG(&adapter->hw, IMC, 0xffffffff); in ixgb_up()
220 IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT); in ixgb_up()
228 IXGB_WRITE_REG(hw, CTRL0, ctrl0); in ixgb_up()
285 IXGB_WRITE_REG(hw, MFS, hw->max_frame_size << IXGB_MFS_SHIFT); in ixgb_reset()
291 IXGB_WRITE_REG(hw, CTRL0, ctrl0); in ixgb_reset()
704 IXGB_WRITE_REG(hw, TDBAL, (tdba & 0x00000000ffffffffULL)); in ixgb_configure_tx()
705 IXGB_WRITE_REG(hw, TDBAH, (tdba >> 32)); in ixgb_configure_tx()
707 IXGB_WRITE_REG(hw, TDLEN, tdlen); in ixgb_configure_tx()
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Dixgb_osdep.h23 #define IXGB_WRITE_REG(a, reg, value) ( \ macro