Searched refs:EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (Results 1 – 1 of 1) sorted by relevance
62 #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0) macro147 *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2; in exynos4x12_rate_to_clk()