Searched refs:CLK_TOP_MSDC50_0_SEL (Results 1 – 16 of 16) sorted by relevance
| /linux-5.19.10/include/dt-bindings/clock/ |
| D | mt7629-clk.h | 94 #define CLK_TOP_MSDC50_0_SEL 84 macro
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| D | mt7622-clk.h | 79 #define CLK_TOP_MSDC50_0_SEL 67 macro
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| D | mt6765-clk.h | 144 #define CLK_TOP_MSDC50_0_SEL 109 macro
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| D | mt8173-clk.h | 106 #define CLK_TOP_MSDC50_0_SEL 96 macro
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| D | mt2712-clk.h | 143 #define CLK_TOP_MSDC50_0_SEL 112 macro
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| D | mt8192-clk.h | 36 #define CLK_TOP_MSDC50_0_SEL 24 macro
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| /linux-5.19.10/Documentation/devicetree/bindings/mmc/ |
| D | mtk-sd.yaml | 203 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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| /linux-5.19.10/drivers/clk/mediatek/ |
| D | clk-mt7629.c | 512 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
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| D | clk-mt7622.c | 542 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
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| D | clk-mt2712.c | 768 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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| D | clk-mt6765.c | 410 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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| D | clk-mt8173.c | 560 MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", msdc50_0_parents, 0x0070, 16, 4, 23),
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| D | clk-mt8192.c | 766 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
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| /linux-5.19.10/arch/arm64/boot/dts/mediatek/ |
| D | mt8173-elm.dtsi | 382 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
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| D | mt7622.dtsi | 706 <&topckgen CLK_TOP_MSDC50_0_SEL>;
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| D | mt8192.dtsi | 1130 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
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