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Searched refs:CLK_TOP_APLL12_CK_DIV0 (Results 1 – 5 of 5) sorted by relevance

/linux-5.19.10/include/dt-bindings/clock/
Dmt8516-clk.h196 #define CLK_TOP_APLL12_CK_DIV0 164 macro
Dmt8186-clk.h150 #define CLK_TOP_APLL12_CK_DIV0 131 macro
/linux-5.19.10/drivers/clk/mediatek/
Dclk-mt8186-topckgen.c675 DIV_GATE(CLK_TOP_APLL12_CK_DIV0, "apll12_div0", "apll_i2s0_mck_sel",
Dclk-mt8516.c478 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
Dclk-mt8167.c668 DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",