Searched refs:CLK_SCLK_PCIE_100_FSYS (Results 1 – 4 of 4) sorted by relevance
164 #define CLK_SCLK_PCIE_100_FSYS 228 macro
991 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
437 <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
656 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",