Searched refs:shadow_regs (Results 1 – 6 of 6) sorted by relevance
80 u8 shadow_regs[MAX8660_N_REGS]; /* as chip is write only */ member90 u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; in max8660_write()97 max8660->shadow_regs[reg] = reg_val; in max8660_write()110 u8 val = max8660->shadow_regs[MAX8660_OVER1]; in max8660_dcdc_is_enabled()140 u8 selector = max8660->shadow_regs[reg]; in max8660_dcdc_get()196 u8 selector = max8660->shadow_regs[MAX8660_MDTV2]; in max8660_ldo5_get()243 u8 val = max8660->shadow_regs[MAX8660_OVER2]; in max8660_ldo67_is_enabled()273 u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf; in max8660_ldo67_get()383 max8660->shadow_regs[MAX8660_OVER1] = 5; in max8660_probe()395 max8660->shadow_regs[MAX8660_ADTV1] = in max8660_probe()[all …]
47 struct cbe_pmd_shadow_regs *shadow_regs; \49 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \51 shadow_regs->reg = _x; \56 struct cbe_pmd_shadow_regs *shadow_regs; \57 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); \58 (val) = shadow_regs->reg; \94 struct cbe_pmd_shadow_regs *shadow_regs; in cbe_write_phys_ctr() local112 shadow_regs = cbe_get_cpu_pmd_shadow_regs(cpu); in cbe_write_phys_ctr()113 shadow_regs->counter_value_in_latch |= (1 << phys_ctr); in cbe_write_phys_ctr()310 struct cbe_pmd_shadow_regs *shadow_regs; in cbe_enable_pm() local[all …]
505 struct shadow_regs *shadow_regs; member
568 ha->shadow_regs = NULL; in DEF_SCSI_QCMD()601 sizeof(struct shadow_regs) + in qla4xxx_mem_alloc()634 ha->shadow_regs = (struct shadow_regs *) (ha->queues + align + in qla4xxx_mem_alloc()1584 return (uint16_t)le32_to_cpu(ha->shadow_regs->req_q_out); in qla4xxx_rd_shdw_req_q_out()1594 return (uint16_t)le32_to_cpu(ha->shadow_regs->rsp_q_in); in qla4xxx_rd_shdw_rsp_q_in()
146 ha->shadow_regs->req_q_out = __constant_cpu_to_le32(0); in qla4xxx_init_rings()147 ha->shadow_regs->rsp_q_in = __constant_cpu_to_le32(0); in qla4xxx_init_rings()
205 struct shadow_regs { struct