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Searched refs:rFPGA0_XA_HSSIParameter2 (Results 1 – 7 of 7) sorted by relevance

/linux-2.6.39/drivers/staging/rtl8712/
Drtl871x_mp.c424 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); in r8712_SwitchAntenna()
431 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); in r8712_SwitchAntenna()
438 set_bb_reg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); in r8712_SwitchAntenna()
Drtl871x_mp_phy_regdef.h92 #define rFPGA0_XA_HSSIParameter2 0x824 macro
/linux-2.6.39/drivers/staging/rtl8192u/
Dr819xU_phyreg.h47 #define rFPGA0_XA_HSSIParameter2 0x824 macro
Dr819xU_phy.c630 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 in rtl8192_InitBBRFRegDef()
820 priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); in rtl8192_BB_Config_ParaFile()
/linux-2.6.39/drivers/staging/rtl8192e/
Dr819xE_phyreg.h53 #define rFPGA0_XA_HSSIParameter2 0x824 macro
Dr819xE_phy.c1162 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 in rtl8192_InitBBRFRegDef()
Dr8192E_core.c4017 priv->phy_reg824_bit9 = rtl8192_QueryBBReg(priv, rFPGA0_XA_HSSIParameter2, 0x200); in rtl8192_query_rxphystatus()