| /linux-2.6.39/arch/sh/kernel/ |
| D | traps_32.c | 184 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, in handle_unaligned_ins() argument
192 index = (instruction>>8)&15; /* 0x0F00 */ in handle_unaligned_ins()
195 index = (instruction>>4)&15; /* 0x00F0 */ in handle_unaligned_ins()
198 count = 1<<(instruction&3); in handle_unaligned_ins()
208 switch (instruction>>12) { in handle_unaligned_ins()
210 if (instruction & 8) { in handle_unaligned_ins()
242 dstu += (instruction&0x000F)<<2; in handle_unaligned_ins()
250 if (instruction & 4) in handle_unaligned_ins()
264 srcu += (instruction & 0x000F) << 2; in handle_unaligned_ins()
275 if (instruction & 4) in handle_unaligned_ins()
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| D | io_trapped.c | 275 insn_size_t instruction; in handle_trapped_io() local
287 if (copy_from_user(&instruction, (void *)(regs->pc), in handle_trapped_io()
288 sizeof(instruction))) { in handle_trapped_io()
293 tmp = handle_unaligned_access(instruction, regs, in handle_trapped_io()
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| /linux-2.6.39/arch/arm/nwfpe/ |
| D | entry.S | 88 beq next @ get the next instruction;
91 bl EmulateAll @ emulate the instruction
96 .Lx1: ldrt r6, [r5], #4 @ get the next instruction and
113 @ plain LDR instruction. Weird, but it seems harmless.
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| D | fpmodule.inl | 24 /* Note: The CPU thinks it has dealt with the current instruction.
26 instruction, and points 4 bytes beyond the actual instruction
27 that caused the invalid instruction trap to occur. We adjust
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| /linux-2.6.39/arch/frv/kernel/ |
| D | cmode.S | 88 # (4) Preload a series of following instructions to the instruction
111 # (5) Flush the content of all caches by the DCEF instruction.
123 # (8) Execute memory barrier instruction (MEMBAR).
132 # (10) Execute memory barrier instruction (MEMBAR).
144 # (13) Execute the instruction just after the memory barrier
145 # instruction that executes the self-loop 256 times. (Meanwhile,
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| /linux-2.6.39/Documentation/ |
| D | kprobes.txt | 30 on virtually any instruction in the kernel. A jprobe is inserted at
58 instruction and replaces the first byte(s) of the probed instruction
59 with a breakpoint instruction (e.g., int3 on i386 and x86_64).
61 When a CPU hits the breakpoint instruction, a trap occurs, the CPU's
67 Next, Kprobes single-steps its copy of the probed instruction.
68 (It would be simpler to single-step the actual instruction in place,
70 instruction. This would open a small time window when another CPU
73 After the instruction is single-stepped, Kprobes executes the
75 Execution then continues with the instruction following the probepoint.
88 Kprobes then points the saved instruction pointer at the jprobe's
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| /linux-2.6.39/arch/m68k/fpsp040/ |
| D | bugfix.S | 247 | dest and the dest of the xu. We must clear the instruction in
248 | the cu and restore the state, allowing the instruction in the
249 | xu to complete. Remember, the instruction in the nu
251 | If the result of the xu instruction is not exceptional, we can
252 | restore the instruction from the cu to the frame and continue
275 | Check if the instruction which just completed was exceptional.
280 | It is necessary to isolate the result of the instruction in the
369 | dest and the dest of the xu. We must clear the instruction in
370 | the cu and restore the state, allowing the instruction in the
371 | xu to complete. Remember, the instruction in the nu
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| D | smovecr.S | 5 | offset given in the instruction field.
7 | Input: An offset in the instruction word.
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| /linux-2.6.39/Documentation/arm/nwfpe/ |
| D | NOTES | 8 often uses an stfe instruction to save f4 on the stack upon entry to a
9 function, and an ldfe instruction to restore it before returning.
15 This is a side effect of the stfe instruction. The double in f4 had to be
29 in extended precision, due to the stfe instruction used to save f4 in log(y).
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| /linux-2.6.39/arch/m68k/ifpsp060/src/ |
| D | isp.S | 1218 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1219 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1230 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1231 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1242 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1243 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1254 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1255 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
1266 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1267 addq.l &0x2,EXC_EXTWPTR(%a6) # incr instruction ptr
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| D | pfpsp.S | 1228 # the FPIAR holds the "current PC" of the faulting instruction
1232 mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
1233 addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
1234 bsr.l _imem_read_long # fetch the instruction words
1722 # three instruction exceptions don't update the stack pointer. so, if the
2038 # The opclass two PACKED instruction that took an "Unimplemented Data Type"
2371 # _imem_read_long() - read instruction longword #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2404 # (2) The "fmovm.x" instruction w/ dynamic register specification. #
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| /linux-2.6.39/drivers/acpi/apei/ |
| D | apei-base.c | 182 if (entry->instruction >= ctx->instructions || in apei_exec_run()
183 !ctx->ins_table[entry->instruction].run) { in apei_exec_run()
186 entry->instruction); in apei_exec_run()
189 run = ctx->ins_table[entry->instruction].run; in apei_exec_run()
221 ins = entry->instruction; in apei_exec_for_each_entry()
242 u8 ins = entry->instruction; in pre_map_gar_callback()
275 u8 ins = entry->instruction; in post_unmap_gar_callback()
561 u8 ins = entry->instruction; in collect_res_callback()
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| /linux-2.6.39/arch/powerpc/lib/ |
| D | code-patching.c | 32 unsigned int instruction; in create_branch() local
44 instruction = 0x48000000 | (flags & 0x3) | (offset & 0x03FFFFFC); in create_branch()
46 return instruction; in create_branch()
52 unsigned int instruction; in create_cond_branch() local
64 instruction = 0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC); in create_cond_branch()
66 return instruction; in create_cond_branch()
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| /linux-2.6.39/drivers/scsi/aic7xxx_old/ |
| D | sequencer.h | 106 struct instruction { struct
111 struct instruction *stqe_next; argument
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| /linux-2.6.39/arch/arm/kernel/ |
| D | entry-armv.S | 193 @ restore SPSR and restart the instruction
247 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
257 @ the instruction, or the more conventional lr if we are to treat
258 @ this as a real undefined instruction
260 @ r0 - instruction
265 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
267 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
283 @ restore SPSR and restart the instruction
301 mov r0, r2 @ pass address of aborted instruction.
320 @ restore SPSR and restart the instruction
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| /linux-2.6.39/arch/powerpc/xmon/ |
| D | ppc.h | 179 (unsigned long instruction, long op, int dialect, const char **errmsg);
198 long (*extract) (unsigned long instruction, int dialect, int *invalid);
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| /linux-2.6.39/arch/xtensa/kernel/ |
| D | align.S | 208 __src_b a4, a4, a5 # a4 has the instruction
287 1: wsr a7, EPC_1 # skip load instruction
330 1: # a7: instruction pointer, a4: instruction, a3: value
335 addi a7, a7, 2 # incr. PC,assume 16-bit instruction
341 addi a7, a7, 1 # increment PC, 32-bit instruction
343 addi a7, a7, 3 # increment PC, 32-bit instruction
367 1: wsr a7, EPC_1 # skip store instruction
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| /linux-2.6.39/arch/m68k/ifpsp060/ |
| D | CHANGES | 41 3) For an opclass three FP instruction where the effective addressing
62 next instruction, and the result created in fp0 will be
78 For instruction read access errors, the info stacked is:
80 PC = PC of instruction being emulated
82 ADDRESS = PC of instruction being emulated
102 PC = PC of instruction being emulated
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| D | ilsp.doc | 35 and the "cmp2" instruction. These instructions are not
71 function. A branch instruction located at the selected entry point
78 For example, to use a 64-bit multiply instruction,
115 An example of using the "cmp2" instruction is as follows:
128 If the instruction being emulated is a divide and the source
130 instruction, executes an implemented divide using a zero
133 point to the correct instruction, the user will at least be able
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| D | fskeleton.S | 111 | instruction.
130 | instruction.
149 | instruction.
168 | instruction.
189 | bit in the FPSR, and does an "rte". The instruction that caused the
227 | frame to the PC of the instruction causing the exception, and does an "rte".
228 | The execution of the instruction then proceeds with an enabled floating-point
245 | This is the exit point for the 060FPSP when an emulated "ftrapcc" instruction
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| /linux-2.6.39/drivers/scsi/aic7xxx/aicasm/ |
| D | aicasm.c | 100 static STAILQ_HEAD(,instruction) seq_program;
322 struct instruction *cur_instr; in back_patch()
351 struct instruction *cur_instr; in output_code()
524 struct instruction *cur_instr; in output_listing()
732 struct instruction *
735 struct instruction *new_instr; in seq_alloc()
737 new_instr = (struct instruction *)malloc(sizeof(struct instruction)); in seq_alloc()
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| /linux-2.6.39/arch/s390/kernel/ |
| D | mcount64.S | 42 # The bras instruction gets runtime patched to call prepare_ftrace_return.
43 # See ftrace_enable_ftrace_graph_caller. The patched instruction is:
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| D | mcount.S | 46 # The bras instruction gets runtime patched to call prepare_ftrace_return.
47 # See ftrace_enable_ftrace_graph_caller. The patched instruction is:
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| /linux-2.6.39/arch/arm/mm/ |
| D | abort-lv4t.S | 31 ldr r8, [r2] @ read arm instruction
76 and r5, r8, #15 << 16 @ Extract 'n' from instruction
94 and r5, r8, #15 << 16 @ Extract 'n' from instruction
108 and r5, r8, #15 << 16 @ Extract 'n' from instruction
120 and r7, r8, #15 @ Extract 'm' from instruction
162 ldrh r8, [r2] @ read instruction
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| /linux-2.6.39/arch/mips/include/asm/mach-cavium-octeon/ |
| D | kernel-entry-init.h | 48 # Disable instruction prefetching (Octeon Pass1 errata)
53 # Reenable instruction prefetching, not on Pass1
63 # CN30XX Disable instruction prefetching
|