Searched refs:RD_REG_WORD (Results 1 – 11 of 11) sorted by relevance
29 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()32 data = RD_REG_WORD(®->nvram); in qla2x00_lock_nvram_access()37 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()39 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()44 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()46 data = RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()62 RD_REG_WORD(®->u.isp2300.host_semaphore); in qla2x00_unlock_nvram_access()77 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()81 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()84 RD_REG_WORD(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()[all …]
88 mb0 = RD_REG_WORD(®->mailbox0); in qla24xx_dump_ram()188 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); in qla24xx_soft_reset()191 mb0 = (uint32_t) RD_REG_WORD(®->mailbox0); in qla24xx_soft_reset()206 for (cnt = 30000; RD_REG_WORD(®->mailbox0) != 0 && in qla24xx_soft_reset()267 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()277 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()283 RD_REG_WORD(®->hccr); in qla2xxx_dump_ram()308 *buf++ = htons(RD_REG_WORD(dmp_reg++)); in qla2xxx_read_window()437 fw->hccr = htons(RD_REG_WORD(®->hccr)); in qla2300_fw_dump()443 (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && in qla2300_fw_dump()[all …]
25 first = RD_REG_WORD(addr); in qla2x00_debounce_register()28 second = RD_REG_WORD(addr); in qla2x00_debounce_register()
59 hccr = RD_REG_WORD(®->hccr); in qla2100_intr_handler()70 RD_REG_WORD(®->hccr); in qla2100_intr_handler()75 } else if ((RD_REG_WORD(®->istatus) & ISR_RISC_INT) == 0) in qla2100_intr_handler()78 if (RD_REG_WORD(®->semaphore) & BIT_0) { in qla2100_intr_handler()80 RD_REG_WORD(®->hccr); in qla2100_intr_handler()100 RD_REG_WORD(®->semaphore); in qla2100_intr_handler()105 RD_REG_WORD(®->hccr); in qla2100_intr_handler()161 hccr = RD_REG_WORD(®->hccr); in qla2300_intr_handler()175 RD_REG_WORD(®->hccr); in qla2300_intr_handler()259 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla2x00_mbx_completion()[all …]
611 ha->pci_attr = RD_REG_WORD(®->ctrl_status); in qla2100_pci_config()655 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2300_pci_config()663 RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()673 RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()678 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0) in qla2300_pci_config()693 ha->pci_attr = RD_REG_WORD(®->ctrl_status); in qla2300_pci_config()846 if ((RD_REG_WORD(®->hccr) & in qla2x00_reset_chip()852 RD_REG_WORD(®->hccr); /* PCI Posting. */ in qla2x00_reset_chip()858 RD_REG_WORD(®->ctrl_status); /* PCI Posting. */ in qla2x00_reset_chip()862 RD_REG_WORD(®->fpm_diag_config); /* PCI Posting. */ in qla2x00_reset_chip()[all …]
1966 ha->mailbox_out[cnt] = RD_REG_WORD(wptr); in qla82xx_mbx_completion()2048 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_intr_handler()2049 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_intr_handler()2050 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_intr_handler()2122 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_msix_default()2123 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_msix_default()2124 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_msix_default()2218 mb[1] = RD_REG_WORD(®->mailbox_out[1]); in qla82xx_poll()2219 mb[2] = RD_REG_WORD(®->mailbox_out[2]); in qla82xx_poll()2220 mb[3] = RD_REG_WORD(®->mailbox_out[3]); in qla82xx_poll()
107 #define RD_REG_WORD(addr) readw(addr) macro482 RD_REG_WORD(MAILBOX_REG(ha, reg, num))491 RD_REG_WORD(FB_CMD_REG(ha, reg))
258 mb0 = RD_REG_WORD(®->isp24.mailbox0); in qla2x00_mailbox_command()262 ictrl = RD_REG_WORD(®->isp.ictrl); in qla2x00_mailbox_command()3987 mb0 = RD_REG_WORD(®->mailbox0); in qla81xx_write_mpi_register()
1396 RD_REG_WORD(®->ictrl); in qla2x00_enable_intrs()1411 RD_REG_WORD(®->ictrl); in qla2x00_disable_intrs()
775 ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); in qla1280_mailbox_timeout()778 RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); in qla1280_mailbox_timeout()876 RD_REG_WORD(&ha->iobase->istatus)); in qla1280_error_action()879 RD_REG_WORD(&ha->iobase->host_cmd), in qla1280_error_action()880 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()1099 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()1107 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()1479 RD_REG_WORD(®->host_cmd); in qla1280_initialize_adapter()1628 data = RD_REG_WORD(®->ictrl); in qla1280_chip_diag()1644 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_chip_diag()[all …]
60 #define RD_REG_WORD(addr) readw_relaxed(addr) macro64 #define RD_REG_WORD(addr) inw((unsigned long)addr) macro65 #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr)