Searched refs:OUTMODE_MPEG2_PAR_GATED_CLK (Results 1 – 8 of 8) sorted by relevance
154 #define OUTMODE_MPEG2_PAR_GATED_CLK 1 macro
198 case OUTMODE_MPEG2_PAR_GATED_CLK: in to_fw_output_mode()1485 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib9000_fw_set_output_mode()1511 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib9000_fw_set_output_mode()2281 …tput_mode != OUTMODE_MPEG2_SERIAL) && (st->chip.d9.cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) in dib9000_attach()
132 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib7000p_set_output_mode()2167 case OUTMODE_MPEG2_PAR_GATED_CLK: in dib7090_set_output_mode()2289 …->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (st->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) in dib7000p_attach()
169 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock in dib3000mc_set_output_mode()
268 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock in dib8000_set_output_mode()2528 …fg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK)) in dib8000_attach()
123 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock in dib7000m_set_output_mode()
2242 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,2269 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,
1002 .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK,