| /linux-2.6.39/arch/sh/kernel/cpu/sh4a/ |
| D | hwblk-sh7724.c | 31 #define MSTPCR2 0xa4150038 macro
75 [HWBLK_MMC] = HWBLK(MSTPCR2, 29, CORE_AREA),
76 [HWBLK_ETHER] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
77 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 26, CORE_AREA_BM),
78 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
79 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
80 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
81 [HWBLK_USB1] = HWBLK(MSTPCR2, 21, CORE_AREA),
82 [HWBLK_USB0] = HWBLK(MSTPCR2, 20, CORE_AREA),
83 [HWBLK_2DG] = HWBLK(MSTPCR2, 19, CORE_AREA_BM),
[all …]
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| D | hwblk-sh7723.c | 31 #define MSTPCR2 0xa4150038 macro
75 [HWBLK_ATAPI] = HWBLK(MSTPCR2, 28, CORE_AREA_BM),
76 [HWBLK_ADC] = HWBLK(MSTPCR2, 27, CORE_AREA),
77 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
78 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
79 [HWBLK_TSIF] = HWBLK(MSTPCR2, 22, CORE_AREA),
80 [HWBLK_ICB] = HWBLK(MSTPCR2, 21, CORE_AREA_BM),
81 [HWBLK_SDHI0] = HWBLK(MSTPCR2, 18, CORE_AREA),
82 [HWBLK_SDHI1] = HWBLK(MSTPCR2, 17, CORE_AREA),
83 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
[all …]
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| D | hwblk-sh7722.c | 31 #define MSTPCR2 0xa4150038 macro
67 [HWBLK_TPU] = HWBLK(MSTPCR2, 25, CORE_AREA),
68 [HWBLK_IRDA] = HWBLK(MSTPCR2, 24, CORE_AREA),
69 [HWBLK_SDHI] = HWBLK(MSTPCR2, 18, CORE_AREA),
70 [HWBLK_SIM] = HWBLK(MSTPCR2, 16, CORE_AREA),
71 [HWBLK_KEYSC] = HWBLK(MSTPCR2, 14, SUB_AREA),
72 [HWBLK_TSIF] = HWBLK(MSTPCR2, 13, SUB_AREA),
73 [HWBLK_USBF] = HWBLK(MSTPCR2, 11, CORE_AREA),
74 [HWBLK_2DG] = HWBLK(MSTPCR2, 9, CORE_AREA_BM),
75 [HWBLK_SIU] = HWBLK(MSTPCR2, 8, CORE_AREA),
[all …]
|
| D | clock-sh7343.c | 35 #define MSTPCR2 0xa4150038 macro
178 [MSTP225] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 25, 0),
179 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
180 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
181 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
182 [MSTP216] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 16, 0),
183 [MSTP214] = MSTP(&r_clk, MSTPCR2, 14, 0),
184 [MSTP213] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 13, 0),
185 [MSTP212] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 12, 0),
186 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
[all …]
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| D | clock-sh7366.c | 35 #define MSTPCR2 0xa4150038 macro
178 [MSTP227] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 27, 0),
179 [MSTP226] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 26, 0),
180 [MSTP224] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 24, 0),
181 [MSTP223] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 23, 0),
182 [MSTP222] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 22, 0),
183 [MSTP218] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 18, 0),
184 [MSTP217] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 17, 0),
185 [MSTP211] = MSTP(&div4_clks[DIV4_P], MSTPCR2, 11, 0),
186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
[all …]
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| D | clock-sh7757.c | 80 #define MSTPCR2 0xffc10028 macro
101 [MSTP220] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 20, 0),
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| /linux-2.6.39/arch/sh/boot/romimage/ |
| D | mmcif-sh7724.c | 17 #define MSTPCR2 0xa4150038 macro
36 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
69 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); in mmcif_loader()
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| /linux-2.6.39/arch/sh/include/cpu-sh4/cpu/ |
| D | freq.h | 24 #define MSTPCR2 0xa4150038 macro
48 #define MSTPCR2 0xa4150038 macro
|