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Searched refs:MSTPCR1 (Results 1 – 12 of 12) sorted by relevance

/linux-2.6.39/arch/sh/kernel/cpu/sh4a/
Dclock-sh7757.c79 #define MSTPCR1 0xffc80034 macro
92 [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
93 [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
94 [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
95 [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
96 [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
97 [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
98 [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
Dclock-sh7786.c83 #define MSTPCR1 0xffc40034 macro
118 [MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
119 [MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
120 [MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
121 [MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
122 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
123 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
124 [MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
125 [MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
Dhwblk-sh7724.c30 #define MSTPCR1 0xa4150034 macro
70 [HWBLK_KEYSC] = HWBLK(MSTPCR1, 12, SUB_AREA),
71 [HWBLK_RTC] = HWBLK(MSTPCR1, 11, SUB_AREA),
72 [HWBLK_IIC0] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_IIC1] = HWBLK(MSTPCR1, 8, CORE_AREA),
Dclock-sh7785.c84 #define MSTPCR1 0xffc80034 macro
112 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
113 [MSTP117] = SH_CLK_MSTP32(NULL, MSTPCR1, 17, 0),
114 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
115 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
116 [MSTP100] = SH_CLK_MSTP32(NULL, MSTPCR1, 0, 0),
Dclock-shx3.c77 #define MSTPCR1 0xffc00034 macro
98 [MSTP119] = SH_CLK_MSTP32(NULL, MSTPCR1, 19, 0),
99 [MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
100 [MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
Dhwblk-sh7722.c30 #define MSTPCR1 0xa4150034 macro
64 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
65 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
Dhwblk-sh7723.c30 #define MSTPCR1 0xa4150034 macro
72 [HWBLK_IIC] = HWBLK(MSTPCR1, 9, CORE_AREA),
73 [HWBLK_RTC] = HWBLK(MSTPCR1, 8, SUB_AREA),
Dclock-sh7343.c34 #define MSTPCR1 0xa4150034 macro
175 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
176 [MSTP108] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 8, 0),
Dclock-sh7366.c34 #define MSTPCR1 0xa4150034 macro
176 [MSTP109] = MSTP(&div4_clks[DIV4_P], MSTPCR1, 9, 0),
/linux-2.6.39/arch/sh/include/cpu-sh4/cpu/
Dfreq.h23 #define MSTPCR1 0xa4150034 macro
47 #define MSTPCR1 0xa4150034 macro
/linux-2.6.39/arch/sh/boards/mach-sh7763rdp/
Dsetup.c208 __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1); in sh7763rdp_setup()
/linux-2.6.39/arch/sh/include/mach-common/mach/
Dsh7763rdp.h18 #define MSTPCR1 0xFFC80038 macro