Searched refs:FEAT_REG_DSIPLL_REGM (Results 1 – 3 of 3) sorted by relevance
67 [FEAT_REG_DSIPLL_REGM] = { 0, 0 },82 [FEAT_REG_DSIPLL_REGM] = { 18, 8 },97 [FEAT_REG_DSIPLL_REGM] = { 20, 9 },
56 FEAT_REG_DSIPLL_REGM, enumerator
1321 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); in dsi_pll_set_clock_div()