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Searched refs:DPLL_CTL (Results 1 – 6 of 6) sorted by relevance

/linux-2.6.39/arch/arm/mach-omap1/
Dreset.c18 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in omap1_arch_reset()
Dsram.S25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
Dboard-voiceblue.c241 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in voiceblue_reset()
Dclock_data.c832 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
843 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
870 omap_writew(0x2290, DPLL_CTL); in omap1_clk_init()
/linux-2.6.39/arch/arm/plat-tcc/include/mach/
Dhardware.h41 #define DPLL_CTL 0xfffecf00 macro
/linux-2.6.39/arch/arm/plat-omap/include/plat/
Dhardware.h89 #define DPLL_CTL (0xfffecf00) macro