Searched refs:BIT_5 (Results 1 – 13 of 13) sorted by relevance
31 #define BIT_5 0x20 macro134 #define ISP_CFG0_1040C BIT_5 /* ISP1040C */137 #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */138 #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */319 #define TP_PPR BIT_5 /* PPR */
481 return BIT_5; in qla1280_data_direction()485 return BIT_5 | BIT_6; in qla1280_data_direction()1961 status = qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_5 | in qla1280_init_rings()2230 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()2310 mb[1] |= BIT_5; in qla1280_nvram_config()2315 mb[2] |= BIT_5; in qla1280_nvram_config()3997 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2) in qla1280_get_target_parameters()
63 #define BIT_5 0x20 macro226 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */398 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */593 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5614 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5744 #define MBX_5 BIT_51258 #define CF_READ BIT_51352 #define PO_DISABLE_INCR_REF_TAG BIT_51431 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */2512 #define DT_ISP6312 BIT_5[all …]
19 #define FO2_ENABLE_SEL_CLASS2 BIT_536 #define PDF_FCP2_CONF BIT_5745 #define LCF_SKIP_PRLI BIT_5 /* Skip PRLI after PLOGI. */746 #define LCF_IMPL_LOGO_ALL BIT_5 /* Implicit LOGO to all ports. */919 #define CSRX_MAX_WRT_BURST_MASK (BIT_5|BIT_4)960 #define HCCRX_RISC_RESET BIT_5 /* RISC Reset mode bit. */
1619 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()1626 ha->fw_options[10] |= BIT_5 | in qla2x00_update_fw_options()1632 (BIT_7 | BIT_6 | BIT_5)) >> 5; in qla2x00_update_fw_options()1637 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; in qla2x00_update_fw_options()1644 ha->fw_options[11] |= BIT_5 | in qla2x00_update_fw_options()2243 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()2244 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()2245 nv->add_firmware_options[1] = BIT_5 | BIT_4; in qla2x00_nvram_config()2250 nv->firmware_options[1] = BIT_7 | BIT_5; in qla2x00_nvram_config()2251 nv->add_firmware_options[0] = BIT_5; in qla2x00_nvram_config()[all …]
645 options |= BIT_5; in qla25xx_create_req_que()742 options |= BIT_5; in qla25xx_create_rsp_que()
2878 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); in qla2x00_set_idma_speed()3009 vpmod->options_idx1 = BIT_3|BIT_4|BIT_5; in qla24xx_modify_vp_config()
1877 if ((flash_data & BIT_5) && cnt > 2) in qla2x00_poll_flash()
1224 } else if (iop[0] & BIT_5) in qla24xx_logio_entry()
424 (BIT_4 | BIT_5 | BIT_6 | BIT_7 | BIT_8 | BIT_9)) >> 4; in qla24xx_pci_info_str()
990 arg1 |= (BIT_2 | BIT_5); in qlcnic_config_switch_port()994 arg1 |= (BIT_3 | BIT_5); in qlcnic_config_switch_port()1036 esw_cfg->host_vlan_tag = !!(arg1 & BIT_5); in qlcnic_get_eswitch_port_config()
199 #define BIT_5 0x20 macro
70 #define BIT_5 0x20 macro