| /linux-2.4.37.9/drivers/scsi/ |
| D | g_NCR5380.c | 854 …for (i = 0; (phases[i].value != PHASE_UNKNOWN) && (phases[i].value != (status & PHASE_MASK)); ++i); in generic_NCR5380_proc_info()
855 PRINTP("Phase %s\n" ANDP phases[i].name); in generic_NCR5380_proc_info()
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| D | AM53C974.c | 398 } phases[] = { variable
437 for (i = 0; (phases[i].value != PHASE_RES_1) && in AM53C974_print_phase()
438 (phases[i].value != (statreg & STATREG_PHASE)); ++i); in AM53C974_print_phase()
440 printk("scsi%d : phase %s, latched at end of last command\n", instance->host_no, phases[i].name); in AM53C974_print_phase()
442 printk("scsi%d : phase %s, real time\n", instance->host_no, phases[i].name); in AM53C974_print_phase()
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| D | atari_NCR5380.c | 588 } phases[] = { variable
610 for (i = 0; (phases[i].value != PHASE_UNKNOWN) && in NCR5380_print_phase()
611 (phases[i].value != (status & PHASE_MASK)); ++i); in NCR5380_print_phase()
612 printk(KERN_DEBUG "scsi%d: phase %s\n", HOSTNO, phases[i].name); in NCR5380_print_phase()
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| D | mac_NCR5380.c | 611 } phases[] = { variable
633 for (i = 0; (phases[i].value != PHASE_UNKNOWN) && in NCR5380_print_phase()
634 (phases[i].value != (status & PHASE_MASK)); ++i); in NCR5380_print_phase()
635 printk(KERN_DEBUG "scsi%d: phase %s\n", HOSTNO, phases[i].name); in NCR5380_print_phase()
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| D | sun3_NCR5380.c | 596 } phases[] = { variable
618 for (i = 0; (phases[i].value != PHASE_UNKNOWN) && in NCR5380_print_phase()
619 (phases[i].value != (status & PHASE_MASK)); ++i); in NCR5380_print_phase()
620 printk(KERN_DEBUG "scsi%d: phase %s\n", HOSTNO, phases[i].name); in NCR5380_print_phase()
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| D | NCR5380.c | 438 } phases[] = { variable
468 …for (i = 0; (phases[i].value != PHASE_UNKNOWN) && (phases[i].value != (status & PHASE_MASK)); ++i); in NCR5380_print_phase()
469 printk("scsi%d : phase %s\n", instance->host_no, phases[i].name); in NCR5380_print_phase()
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| D | 53c7,8xx.scr | 567 ; and DATA_OUT phases are allowed, with the user provided
570 ; phases.
575 ; and DATA OUT phases respectively, with the state of the active
1233 ; specification, we can't change phases until REQ transitions true->false,
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| D | sym53c416.c | 209 enum phases enum
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| D | 53c7xx.scr | 696 ; and DATA_OUT phases are allowed, with the user provided
699 ; phases.
704 ; and DATA OUT phases respectively, with the state of the active
1509 ; specification, we can't change phases until REQ transitions true->false,
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| D | README.st | 167 max_sg_segs) and the number of segments used in phases 1 and 2
172 is smaller than the number of segments used in phases 1 and 2,
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| D | ChangeLog.sym53c8xx | 97 * Simpler handling of illegal phases and data overrun from
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| D | ChangeLog | 327 all DATA IN and DATA OUT phases right. Utilize HBA_interpret flag.
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| /linux-2.4.37.9/drivers/acorn/scsi/ |
| D | fas216.c | 215 static const char *phases[] = { in fas216_bus_phase() local
222 return phases[stat & STAT_BUSMASK]; in fas216_bus_phase()
227 static const char *phases[] = { in fas216_drv_phase() local
241 if (info->scsi.phase < ARRAY_SIZE(phases) && in fas216_drv_phase()
242 phases[info->scsi.phase]) in fas216_drv_phase()
243 return phases[info->scsi.phase]; in fas216_drv_phase()
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| /linux-2.4.37.9/drivers/scsi/aic7xxx/ |
| D | aic7xxx.seq | 475 * Now determine what phases the host wants us
599 * Data phases on the bus are from the
656 * Main loop for information transfer phases. Wait for the
920 * As a target, we control the phases,
1343 * For data-in phases, wait for any pending acks from the
1345 * send Ignore Wide Residue messages for data-in phases.
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| D | aic79xx.seq | 677 * Main loop for information transfer phases. Wait for the
1508 * For data-in phases, wait for any pending acks from the
1510 * send Ignore Wide Residue messages for data-in phases.
1877 * phases that are typically caused by CRC errors in status packet
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| D | aic7xxx.reg | 118 * Possible phases in SCSISIGI
149 * Possible phases to write into SCSISIG0
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| D | aic79xx.reg | 1663 * Possible phases to write into SCSISIG0
1690 * Possible phases in SCSISIGI
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| /linux-2.4.37.9/drivers/scsi/aic7xxx_old/ |
| D | aic7xxx.reg | 112 * Possible phases in SCSISIGI
141 * Possible phases to write into SCSISIG0
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| D | aic7xxx.seq | 264 * for "in" phases
286 * Main loop for information transfer phases. Wait for the target
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| /linux-2.4.37.9/Documentation/ |
| D | initrd.txt | 14 initrd is mainly designed to allow system startup to occur in two phases,
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