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Searched refs:SHADDR (Results 1 – 12 of 12) sorted by relevance

/linux-2.4.37.9/drivers/scsi/aic7xxx_old/
Daic7xxx_reg.h155 #define SHADDR 0x14 macro
Daic7xxx.seq344 bmov HADDR, SHADDR, 4;
902 * and the SCB DATAPTR becomes the current SHADDR.
908 bmov SCB_DATAPTR, SHADDR, 4;
914 mvi SHADDR call bcopy_4;
Daic7xxx.reg391 * manner as STCNT is counted down. SHADDR should always be used
395 register SHADDR {
/linux-2.4.37.9/drivers/scsi/aic7xxx/
Daic7xxx.seq1087 mov SCB_RESIDUAL_DATACNT[3], SHADDR;
1165 * Reload HADDR from SHADDR and setup the
1169 bmov HADDR, SHADDR, 4;
1174 mvi SHADDR call bcopy_4;
1726 * we can only ack the message after SHADDR has been saved. On these
1727 * chips, SHADDR increments with every bus transaction, even PIO.
1754 * and the SCB_DATAPTR becomes the current SHADDR.
1759 bmov SCB_DATAPTR, SHADDR, 4;
1766 mvi SHADDR call bcopy_4;
Daic7xxx.reg416 * manner as STCNT is counted down. SHADDR should always be used
420 register SHADDR {
Daic7xxx_reg.h1221 #define SHADDR 0x14 macro
Daic79xx.seq1158 * The SCB_DATAPTR becomes the current SHADDR.
1162 bmov SCB_DATAPTR, SHADDR, 8;
Daic79xx_reg.h3002 #define SHADDR 0x60 macro
Daic79xx_core.c4447 data_addr = ahd_inq(ahd, SHADDR); in ahd_handle_ign_wide_residue()
8631 ahd_inl(ahd, SHADDR+4), in ahd_dump_card_state()
8632 ahd_inl(ahd, SHADDR), in ahd_dump_card_state()
Daic79xx.reg2436 register SHADDR {
Daic7xxx_core.c3616 data_addr = ahc_inl(ahc, SHADDR); in ahc_handle_ign_wide_residue()
/linux-2.4.37.9/drivers/scsi/
Daic7xxx_old.c5206 cur_addr = aic_inb(p, SHADDR) | (aic_inb(p, SHADDR + 1) << 8) | in aic7xxx_handle_seqint()
5207 (aic_inb(p, SHADDR + 2) << 16) | (aic_inb(p, SHADDR + 3) << 24); in aic7xxx_handle_seqint()
5296 aic_outb(p, cur_addr & 0xff, SHADDR); in aic7xxx_handle_seqint()
5297 aic_outb(p, (cur_addr >> 8) & 0xff, SHADDR + 1); in aic7xxx_handle_seqint()
5298 aic_outb(p, (cur_addr >> 16) & 0xff, SHADDR + 2); in aic7xxx_handle_seqint()
5299 aic_outb(p, (cur_addr >> 24) & 0xff, SHADDR + 3); in aic7xxx_handle_seqint()