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Searched refs:DCRN_SDRAM0_BASE (Results 1 – 2 of 2) sorted by relevance

/linux-2.4.37.9/arch/ppc/platforms/
Dibm405.h319 #ifdef DCRN_SDRAM0_BASE
320 #define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
321 #define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
Dibm405gp.h186 #define DCRN_SDRAM0_BASE 0x010 macro