Searched refs:DCRN_DCRX_BASE (Results 1 – 2 of 2) sorted by relevance
186 #define DCRN_DCRX_BASE 0x020 macro253 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */254 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */255 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */256 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */257 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */258 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */259 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */260 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
182 #define DCRN_DCRX_BASE 0x020 macro243 #define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */244 #define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */245 #define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */246 #define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */247 #define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */248 #define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */249 #define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */250 #define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */