Searched refs:ClrDCSR (Results 1 – 2 of 2) sorted by relevance
44 volatile u_long ClrDCSR; member157 dma->regs->ClrDCSR = in process_dma()228 dma->regs->ClrDCSR = DCSR_ERROR; in dma_irq_handler()231 dma->regs->ClrDCSR = status & (DCSR_DONEA | DCSR_DONEB); in dma_irq_handler()292 regs->ClrDCSR = in sa1100_request_dma()448 dma->regs->ClrDCSR = DCSR_RUN | DCSR_IE; in sa1100_dma_stop()462 dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB|DCSR_DONEA|DCSR_DONEB; in sa1100_dma_stop()503 dma->regs->ClrDCSR = DCSR_STRTA|DCSR_STRTB|DCSR_DONEA|DCSR_DONEB|DCSR_RUN|DCSR_IE; in sa1100_dma_flush_all()581 dma->regs->ClrDCSR = DCSR_RUN | DCSR_IE | DCSR_STRTA | DCSR_STRTB; in sa1100_dma_sleep()604 regs->ClrDCSR = in sa1100_dma_wakeup()
1678 #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..… macro