Searched refs:CSR0_MISS (Results 1 – 11 of 11) sorted by relevance
36 #define CSR0_MISS 0x1000 /* Missed packet (RC) */ macro
22 #define CSR0_MISS 0x1000 /* Missed packet (RC) */ macro
43 #define CSR0_MISS 0x1000 macro
199 …write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0… in am79c961_init_for_open()571 write_rreg(dev->base_addr, CSR0, status & (CSR0_TINT|CSR0_RINT|CSR0_MISS|CSR0_IENA)); in am79c961_interrupt()577 if (status & CSR0_MISS) in am79c961_interrupt()
89 #define CSR0_MISS 0x1000 /* lost Rx block */ macro
230 #define CSR0_MISS 0x1000 /* missed frame (RC) */ macro654 DREG = CSR0_BABL | CSR0_MERR | CSR0_CERR | CSR0_MISS; in lance_interrupt()724 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */ in lance_interrupt()
330 #define CSR0_MISS 0x1000 /* missed frame (RC) */ macro952 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */ in lance_interrupt()962 DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR | in lance_interrupt()
318 #define CSR0_MISS 0x1000 /* missed frame (RC) */ macro1076 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */1086 DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
598 SetLANCE(dev, LANCE_CSR0, oldcsr0 | CSR0_MISS); in irqmiss_handler()792 if ((csr0val & CSR0_MISS) != 0) in irq_handler()
843 if(csr0 & CSR0_MISS) { in ni65_interrupt()1015 if(!(csr0 & CSR0_MISS)) /* don't count errors twice */ in ni65_recv_intr()
1372 if (csr0 & CSR0_MISS) /* No place to store packet ? */ in SK_interrupt()