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Searched refs:wptr (Results 1 – 25 of 127) sorted by relevance

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/linux-6.6.21/drivers/media/usb/pvrusb2/
Dpvrusb2-debugifc.c55 const char *wptr; in debugifc_isolate_word() local
60 wptr = NULL; in debugifc_isolate_word()
68 wptr = buf; in debugifc_isolate_word()
73 *wstrPtr = wptr; in debugifc_isolate_word()
182 const char *wptr; in pvr2_debugifc_do1cmd() local
186 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
189 if (!wptr) return 0; in pvr2_debugifc_do1cmd()
191 pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); in pvr2_debugifc_do1cmd()
192 if (debugifc_match_keyword(wptr,wlen,"reset")) { in pvr2_debugifc_do1cmd()
193 scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); in pvr2_debugifc_do1cmd()
[all …]
/linux-6.6.21/drivers/media/platform/amphion/
Dvpu_rpc.c39 ptr1 = desc->wptr; in vpu_rpc_check_buffer_space()
43 ptr2 = desc->wptr; in vpu_rpc_check_buffer_space()
61 u32 wptr; in vpu_rpc_send_cmd_buf() local
70 wptr = desc->wptr; in vpu_rpc_send_cmd_buf()
71 data = (u32 *)(shared->cmd_mem_vir + desc->wptr - desc->start); in vpu_rpc_send_cmd_buf()
76 wptr += 4; in vpu_rpc_send_cmd_buf()
78 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
79 wptr = desc->start; in vpu_rpc_send_cmd_buf()
85 wptr += 4; in vpu_rpc_send_cmd_buf()
87 if (wptr >= desc->end) { in vpu_rpc_send_cmd_buf()
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Dvpu_malone.c187 u32 wptr; member
318 u32 wptr; member
375 iface->cmd_buffer_desc.buffer.wptr = phy_addr; in vpu_malone_init_rpc()
383 iface->msg_buffer_desc.buffer.wptr = in vpu_malone_init_rpc()
427 iface->eng_access_buff_desc[i].buffer.wptr = in vpu_malone_init_rpc()
450 iface->debug_buffer_desc.buffer.wptr = in vpu_malone_set_log_buf()
502 writel(buf->phys, &str_buf->wptr); in vpu_malone_config_stream_buffer()
519 desc->wptr = readl(&str_buf->wptr); in vpu_malone_get_stream_buffer_desc()
528 static void vpu_malone_update_wptr(struct vpu_malone_str_buffer __iomem *str_buf, u32 wptr) in vpu_malone_update_wptr() argument
532 writel(wptr, &str_buf->wptr); in vpu_malone_update_wptr()
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Dvpu_helpers.c271 u32 *wptr, u32 size, void *src) in vpu_helper_copy_to_stream_buffer() argument
278 if (!stream_buffer || !wptr || !src) in vpu_helper_copy_to_stream_buffer()
284 offset = *wptr; in vpu_helper_copy_to_stream_buffer()
298 *wptr = vpu_helper_step_walk(stream_buffer, offset, size); in vpu_helper_copy_to_stream_buffer()
304 u32 *wptr, u8 val, u32 size) in vpu_helper_memset_stream_buffer() argument
311 if (!stream_buffer || !wptr) in vpu_helper_memset_stream_buffer()
317 offset = *wptr; in vpu_helper_memset_stream_buffer()
335 *wptr = offset; in vpu_helper_memset_stream_buffer()
347 if (desc.rptr > desc.wptr) in vpu_helper_get_free_space()
348 return desc.rptr - desc.wptr; in vpu_helper_get_free_space()
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/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Damdgpu_ih.c152 uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2; in amdgpu_ih_ring_write() local
156 ih->ring[wptr++] = cpu_to_le32(iv[i]); in amdgpu_ih_ring_write()
158 wptr <<= 2; in amdgpu_ih_ring_write()
159 wptr &= ih->ptr_mask; in amdgpu_ih_ring_write()
162 if (wptr != READ_ONCE(ih->rptr)) { in amdgpu_ih_ring_write()
164 WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr)); in amdgpu_ih_ring_write()
167 wptr, ih->rptr); in amdgpu_ih_ring_write()
211 u32 wptr; in amdgpu_ih_process() local
216 wptr = amdgpu_ih_get_wptr(adev, ih); in amdgpu_ih_process()
220 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); in amdgpu_ih_process()
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Diceland_ih.c193 u32 wptr, tmp; in iceland_ih_get_wptr() local
195 wptr = le32_to_cpu(*ih->wptr_cpu); in iceland_ih_get_wptr()
197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
201 wptr = RREG32(mmIH_RB_WPTR); in iceland_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in iceland_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in iceland_ih_get_wptr()
212 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in iceland_ih_get_wptr()
213 ih->rptr = (wptr + 16) & ih->ptr_mask; in iceland_ih_get_wptr()
225 return (wptr & ih->ptr_mask); in iceland_ih_get_wptr()
Dcz_ih.c193 u32 wptr, tmp; in cz_ih_get_wptr() local
195 wptr = le32_to_cpu(*ih->wptr_cpu); in cz_ih_get_wptr()
197 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
201 wptr = RREG32(mmIH_RB_WPTR); in cz_ih_get_wptr()
203 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in cz_ih_get_wptr()
206 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in cz_ih_get_wptr()
213 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cz_ih_get_wptr()
214 ih->rptr = (wptr + 16) & ih->ptr_mask; in cz_ih_get_wptr()
226 return (wptr & ih->ptr_mask); in cz_ih_get_wptr()
Dtonga_ih.c195 u32 wptr, tmp; in tonga_ih_get_wptr() local
197 wptr = le32_to_cpu(*ih->wptr_cpu); in tonga_ih_get_wptr()
199 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
203 wptr = RREG32(mmIH_RB_WPTR); in tonga_ih_get_wptr()
205 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in tonga_ih_get_wptr()
208 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in tonga_ih_get_wptr()
216 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in tonga_ih_get_wptr()
217 ih->rptr = (wptr + 16) & ih->ptr_mask; in tonga_ih_get_wptr()
229 return (wptr & ih->ptr_mask); in tonga_ih_get_wptr()
Dsi_ih.c110 u32 wptr, tmp; in si_ih_get_wptr() local
112 wptr = le32_to_cpu(*ih->wptr_cpu); in si_ih_get_wptr()
114 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in si_ih_get_wptr()
115 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in si_ih_get_wptr()
117 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in si_ih_get_wptr()
118 ih->rptr = (wptr + 16) & ih->ptr_mask; in si_ih_get_wptr()
129 return (wptr & ih->ptr_mask); in si_ih_get_wptr()
Dcik_ih.c191 u32 wptr, tmp; in cik_ih_get_wptr() local
193 wptr = le32_to_cpu(*ih->wptr_cpu); in cik_ih_get_wptr()
195 if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { in cik_ih_get_wptr()
196 wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; in cik_ih_get_wptr()
202 wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); in cik_ih_get_wptr()
203 ih->rptr = (wptr + 16) & ih->ptr_mask; in cik_ih_get_wptr()
214 return (wptr & ih->ptr_mask); in cik_ih_get_wptr()
Dsdma_v5_0.c260 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v5_0_ring_init_cond_exec()
274 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v5_0_ring_patch_cond_exec()
309 u64 wptr; in sdma_v5_0_ring_get_wptr() local
313 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v5_0_ring_get_wptr()
314 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v5_0_ring_get_wptr()
316 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); in sdma_v5_0_ring_get_wptr()
317 wptr = wptr << 32; in sdma_v5_0_ring_get_wptr()
318 wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR)); in sdma_v5_0_ring_get_wptr()
319 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr); in sdma_v5_0_ring_get_wptr()
322 return wptr >> 2; in sdma_v5_0_ring_get_wptr()
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Damdgpu_ring_mux.c214 void amdgpu_ring_mux_set_wptr(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring, u64 wptr) in amdgpu_ring_mux_set_wptr() argument
240 e->sw_wptr = wptr; in amdgpu_ring_mux_set_wptr()
241 e->start_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
244 if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT || mux->wptr_resubmit < wptr) { in amdgpu_ring_mux_set_wptr()
245 amdgpu_ring_mux_copy_pkt_from_sw_ring(mux, ring, e->sw_cptr, wptr); in amdgpu_ring_mux_set_wptr()
246 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
249 e->end_ptr_in_hw_ring = mux->real_ring->wptr; in amdgpu_ring_mux_set_wptr()
341 amdgpu_ring_mux_set_wptr(mux, ring, ring->wptr); in amdgpu_sw_ring_set_wptr_gfx()
429 offset = ring->wptr & ring->buf_mask; in amdgpu_sw_ring_ib_mark_offset()
455 chunk->start = ring->wptr; in amdgpu_ring_mux_start_ib()
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Dsdma_v4_4_2.c176 u64 wptr; in sdma_v4_4_2_ring_get_wptr() local
180 wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); in sdma_v4_4_2_ring_get_wptr()
181 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v4_4_2_ring_get_wptr()
183 wptr = RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR_HI); in sdma_v4_4_2_ring_get_wptr()
184 wptr = wptr << 32; in sdma_v4_4_2_ring_get_wptr()
185 wptr |= RREG32_SDMA(ring->me, regSDMA_GFX_RB_WPTR); in sdma_v4_4_2_ring_get_wptr()
187 ring->me, wptr); in sdma_v4_4_2_ring_get_wptr()
190 return wptr >> 2; in sdma_v4_4_2_ring_get_wptr()
213 lower_32_bits(ring->wptr << 2), in sdma_v4_4_2_ring_set_wptr()
214 upper_32_bits(ring->wptr << 2)); in sdma_v4_4_2_ring_set_wptr()
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Dih_v6_0.c394 u32 wptr, tmp; in ih_v6_0_get_wptr() local
397 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_0_get_wptr()
400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_0_get_wptr()
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_0_get_wptr()
404 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_0_get_wptr()
406 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in ih_v6_0_get_wptr()
412 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_0_get_wptr()
415 wptr, ih->rptr, tmp); in ih_v6_0_get_wptr()
428 return (wptr & ih->ptr_mask); in ih_v6_0_get_wptr()
496 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v6_0_self_irq() local
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Dih_v6_1.c394 u32 wptr, tmp; in ih_v6_1_get_wptr() local
397 wptr = le32_to_cpu(*ih->wptr_cpu); in ih_v6_1_get_wptr()
400 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_1_get_wptr()
403 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in ih_v6_1_get_wptr()
404 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in ih_v6_1_get_wptr()
406 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in ih_v6_1_get_wptr()
412 tmp = (wptr + 32) & ih->ptr_mask; in ih_v6_1_get_wptr()
415 wptr, ih->rptr, tmp); in ih_v6_1_get_wptr()
429 return (wptr & ih->ptr_mask); in ih_v6_1_get_wptr()
497 uint32_t wptr = cpu_to_le32(entry->src_data[0]); in ih_v6_1_self_irq() local
[all …]
Dsdma_v6_0.c90 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ in sdma_v6_0_ring_init_cond_exec()
104 cur = (ring->wptr - 1) & ring->buf_mask; in sdma_v6_0_ring_patch_cond_exec()
138 u64 wptr = 0; in sdma_v6_0_ring_get_wptr() local
142 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr)); in sdma_v6_0_ring_get_wptr()
143 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); in sdma_v6_0_ring_get_wptr()
146 return wptr >> 2; in sdma_v6_0_ring_get_wptr()
175 ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
176 *wptr_saved = ring->wptr << 2; in sdma_v6_0_ring_set_wptr()
178 WDOORBELL64(aggregated_db_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
180 ring->doorbell_index, ring->wptr << 2); in sdma_v6_0_ring_set_wptr()
[all …]
Dvega10_ih.c338 u32 wptr, tmp; in vega10_ih_get_wptr() local
347 wptr = le32_to_cpu(*ih->wptr_cpu); in vega10_ih_get_wptr()
349 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
356 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr); in vega10_ih_get_wptr()
357 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) in vega10_ih_get_wptr()
360 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); in vega10_ih_get_wptr()
366 tmp = (wptr + 32) & ih->ptr_mask; in vega10_ih_get_wptr()
369 wptr, ih->rptr, tmp); in vega10_ih_get_wptr()
383 return (wptr & ih->ptr_mask); in vega10_ih_get_wptr()
/linux-6.6.21/drivers/net/ppp/
Dbsd_comp.c580 unsigned char *wptr; in bsd_compress() local
586 if (wptr) \ in bsd_compress()
588 *wptr++ = (unsigned char) (v); \ in bsd_compress()
591 wptr = NULL; \ in bsd_compress()
630 wptr = obuf; in bsd_compress()
639 if (wptr) in bsd_compress()
641 *wptr++ = PPP_ADDRESS(rptr); in bsd_compress()
642 *wptr++ = PPP_CONTROL(rptr); in bsd_compress()
643 *wptr++ = 0; in bsd_compress()
644 *wptr++ = PPP_COMP; in bsd_compress()
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Dppp_deflate.c190 unsigned char *wptr; in z_compress() local
204 wptr = obuf; in z_compress()
209 wptr[0] = PPP_ADDRESS(rptr); in z_compress()
210 wptr[1] = PPP_CONTROL(rptr); in z_compress()
211 put_unaligned_be16(PPP_COMP, wptr + 2); in z_compress()
212 wptr += PPP_HDRLEN; in z_compress()
213 put_unaligned_be16(state->seqno, wptr); in z_compress()
214 wptr += DEFLATE_OVHD; in z_compress()
216 state->strm.next_out = wptr; in z_compress()
/linux-6.6.21/drivers/net/ethernet/tehuti/
Dtehuti.c171 f->wptr = 0; in bdx_fifo_init()
1101 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_rx_alloc_skbs()
1109 f->m.wptr += sizeof(struct rxf_desc); in bdx_rx_alloc_skbs()
1110 delta = f->m.wptr - f->m.memsz; in bdx_rx_alloc_skbs()
1112 f->m.wptr = delta; in bdx_rx_alloc_skbs()
1121 WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); in bdx_rx_alloc_skbs()
1156 rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); in bdx_recycle_skb()
1164 f->m.wptr += sizeof(struct rxf_desc); in bdx_recycle_skb()
1165 delta = f->m.wptr - f->m.memsz; in bdx_recycle_skb()
1167 f->m.wptr = delta; in bdx_recycle_skb()
[all …]
/linux-6.6.21/drivers/gpu/drm/amd/amdkfd/
Dkfd_kernel_queue.c233 uint32_t wptr, rptr; in kq_acquire_packet_buffer() local
243 wptr = kq->pending_wptr; in kq_acquire_packet_buffer()
249 pr_debug("wptr: %d\n", wptr); in kq_acquire_packet_buffer()
252 available_size = (rptr + queue_size_dwords - 1 - wptr) % in kq_acquire_packet_buffer()
263 if (wptr + packet_size_in_dwords >= queue_size_dwords) { in kq_acquire_packet_buffer()
271 while (wptr > 0) { in kq_acquire_packet_buffer()
272 queue_address[wptr] = kq->nop_packet; in kq_acquire_packet_buffer()
273 wptr = (wptr + 1) % queue_size_dwords; in kq_acquire_packet_buffer()
278 *buffer_ptr = &queue_address[wptr]; in kq_acquire_packet_buffer()
279 kq->pending_wptr = wptr + packet_size_in_dwords; in kq_acquire_packet_buffer()
/linux-6.6.21/drivers/gpu/drm/radeon/
Dradeon_ring.c87 ring->ring_free_dw -= ring->wptr; in radeon_ring_free_size()
128 ring->wptr_old = ring->wptr; in radeon_ring_alloc()
176 while (ring->wptr & ring->align_mask) { in radeon_ring_commit()
214 ring->wptr = ring->wptr_old; in radeon_ring_undo()
314 size = ring->wptr + (ring->ring_size / 4); in radeon_ring_backup()
470 uint32_t rptr, wptr, rptr_next; in radeon_debugfs_ring_info_show() local
476 wptr = radeon_ring_get_wptr(rdev, ring); in radeon_debugfs_ring_info_show()
478 wptr, wptr); in radeon_debugfs_ring_info_show()
492 ring->wptr, ring->wptr); in radeon_debugfs_ring_info_show()
Dvce_v1_0.c98 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_set_wptr()
100 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_set_wptr()
298 WREG32(VCE_RB_RPTR, ring->wptr); in vce_v1_0_start()
299 WREG32(VCE_RB_WPTR, ring->wptr); in vce_v1_0_start()
305 WREG32(VCE_RB_RPTR2, ring->wptr); in vce_v1_0_start()
306 WREG32(VCE_RB_WPTR2, ring->wptr); in vce_v1_0_start()
/linux-6.6.21/drivers/crypto/ccp/
Dtee-dev.c125 tee->rb_mgr.wptr = 0; in tee_init_ring()
260 (tee->rb_mgr.ring_start + tee->rb_mgr.wptr); in tee_submit_cmd()
267 if (!(tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
272 rptr, tee->rb_mgr.wptr); in tee_submit_cmd()
282 (tee->rb_mgr.wptr + sizeof(struct tee_ring_cmd) == rptr || in tee_submit_cmd()
285 rptr, tee->rb_mgr.wptr, cmd->flag); in tee_submit_cmd()
308 tee->rb_mgr.wptr += sizeof(struct tee_ring_cmd); in tee_submit_cmd()
309 if (tee->rb_mgr.wptr >= tee->rb_mgr.ring_size) in tee_submit_cmd()
310 tee->rb_mgr.wptr = 0; in tee_submit_cmd()
313 iowrite32(tee->rb_mgr.wptr, tee->io_regs + tee->vdata->ring_wptr_reg); in tee_submit_cmd()
/linux-6.6.21/drivers/video/fbdev/
Dmaxinefb.c67 unsigned char *wptr; in maxinefb_ims332_write_register() local
69 wptr = regs + 0xa0000 + (regno << 4); in maxinefb_ims332_write_register()
71 *((volatile unsigned short *) (wptr)) = val; in maxinefb_ims332_write_register()

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