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Searched refs:umc_reg_offset (Results 1 – 4 of 4) sorted by relevance

/linux-6.6.21/drivers/gpu/drm/amd/amdgpu/
Dumc_v6_1.c95 uint32_t umc_reg_offset) in umc_v6_1_clear_error_count_per_channel() argument
120 umc_reg_offset) * 4); in umc_v6_1_clear_error_count_per_channel()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
128 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
133 umc_reg_offset) * 4); in umc_v6_1_clear_error_count_per_channel()
137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
149 uint32_t umc_reg_offset = 0; in umc_v6_1_clear_error_count() local
157 umc_reg_offset = get_umc_6_reg_offset(adev, in umc_v6_1_clear_error_count()
162 umc_reg_offset); in umc_v6_1_clear_error_count()
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Dumc_v6_7.c61 uint64_t mc_umc_status, uint32_t umc_reg_offset) in umc_v6_7_query_error_status_helper() argument
70 dev_info(adev->dev, "MCA STATUS 0x%llx, umc_reg_offset 0x%x\n", mc_umc_status, umc_reg_offset); in umc_v6_7_query_error_status_helper()
75 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
77 dev_info(adev->dev, "MCA IPID 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
82 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
84 dev_info(adev->dev, "MCA SYND 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
89 reg_value = RREG64_PCIE((mc_umc_addr + umc_reg_offset) * 4); in umc_v6_7_query_error_status_helper()
91 dev_info(adev->dev, "MCA MISC0 0x%llx, umc_reg_offset 0x%x\n", reg_value, umc_reg_offset); in umc_v6_7_query_error_status_helper()
100 uint32_t umc_reg_offset; in umc_v6_7_ecc_info_query_correctable_error_count() local
103 umc_reg_offset = get_umc_v6_7_reg_offset(adev, in umc_v6_7_ecc_info_query_correctable_error_count()
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Dumc_v8_7.c181 uint32_t umc_reg_offset) in umc_v8_7_clear_error_count_per_channel() argument
193 umc_reg_offset) * 4); in umc_v8_7_clear_error_count_per_channel()
197 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
201 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
206 umc_reg_offset) * 4); in umc_v8_7_clear_error_count_per_channel()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
214 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
222 uint32_t umc_reg_offset = 0; in umc_v8_7_clear_error_count() local
225 umc_reg_offset = get_umc_v8_7_reg_offset(adev, in umc_v8_7_clear_error_count()
230 umc_reg_offset); in umc_v8_7_clear_error_count()
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Dumc_v8_10.c84 uint32_t umc_reg_offset = in umc_v8_10_clear_error_count_per_channel() local
91 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_10_clear_error_count_per_channel()
104 uint32_t umc_reg_offset, in umc_v8_10_query_correctable_error_count() argument
117 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v8_10_query_correctable_error_count()
124 uint32_t umc_reg_offset, in umc_v8_10_query_uncorrectable_error_count() argument
133 mc_umc_status = RREG64_PCIE((mc_umc_status_addr + umc_reg_offset) * 4); in umc_v8_10_query_uncorrectable_error_count()
148 uint32_t umc_reg_offset = in umc_v8_10_query_ecc_error_count() local
152 umc_reg_offset, in umc_v8_10_query_ecc_error_count()
155 umc_reg_offset, in umc_v8_10_query_ecc_error_count()
252 uint32_t umc_reg_offset = in umc_v8_10_query_error_address() local
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