1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * IBM ASM Service Processor Device Driver
4  *
5  * Copyright (C) IBM Corporation, 2004
6  *
7  * Author: Max Asböck <amax@us.ibm.com>
8  */
9 
10 /* Condor service processor specific hardware definitions */
11 
12 #ifndef __IBMASM_CONDOR_H__
13 #define __IBMASM_CONDOR_H__
14 
15 #include <asm/io.h>
16 
17 #define VENDORID_IBM	0x1014
18 #define DEVICEID_RSA	0x010F
19 
20 #define GET_MFA_ADDR(x)  (x & 0xFFFFFF00)
21 
22 #define MAILBOX_FULL(x)  (x & 0x00000001)
23 
24 #define NO_MFAS_AVAILABLE     0xFFFFFFFF
25 
26 
27 #define INBOUND_QUEUE_PORT   0x40  /* contains address of next free MFA */
28 #define OUTBOUND_QUEUE_PORT  0x44  /* contains address of posted MFA    */
29 
30 #define SP_INTR_MASK	0x00000008
31 #define UART_INTR_MASK	0x00000010
32 
33 #define INTR_STATUS_REGISTER   0x13A0
34 #define INTR_CONTROL_REGISTER  0x13A4
35 
36 #define SCOUT_COM_A_BASE         0x0000
37 #define SCOUT_COM_B_BASE         0x0100
38 #define SCOUT_COM_C_BASE         0x0200
39 #define SCOUT_COM_D_BASE         0x0300
40 
sp_interrupt_pending(void __iomem * base_address)41 static inline int sp_interrupt_pending(void __iomem *base_address)
42 {
43 	return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
44 }
45 
uart_interrupt_pending(void __iomem * base_address)46 static inline int uart_interrupt_pending(void __iomem *base_address)
47 {
48 	return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
49 }
50 
ibmasm_enable_interrupts(void __iomem * base_address,int mask)51 static inline void ibmasm_enable_interrupts(void __iomem *base_address, int mask)
52 {
53 	void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
54 	writel( readl(ctrl_reg) & ~mask, ctrl_reg);
55 }
56 
ibmasm_disable_interrupts(void __iomem * base_address,int mask)57 static inline void ibmasm_disable_interrupts(void __iomem *base_address, int mask)
58 {
59 	void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER;
60 	writel( readl(ctrl_reg) | mask, ctrl_reg);
61 }
62 
enable_sp_interrupts(void __iomem * base_address)63 static inline void enable_sp_interrupts(void __iomem *base_address)
64 {
65 	ibmasm_enable_interrupts(base_address, SP_INTR_MASK);
66 }
67 
disable_sp_interrupts(void __iomem * base_address)68 static inline void disable_sp_interrupts(void __iomem *base_address)
69 {
70 	ibmasm_disable_interrupts(base_address, SP_INTR_MASK);
71 }
72 
enable_uart_interrupts(void __iomem * base_address)73 static inline void enable_uart_interrupts(void __iomem *base_address)
74 {
75 	ibmasm_enable_interrupts(base_address, UART_INTR_MASK);
76 }
77 
disable_uart_interrupts(void __iomem * base_address)78 static inline void disable_uart_interrupts(void __iomem *base_address)
79 {
80 	ibmasm_disable_interrupts(base_address, UART_INTR_MASK);
81 }
82 
83 #define valid_mfa(mfa)	( (mfa) != NO_MFAS_AVAILABLE )
84 
get_mfa_outbound(void __iomem * base_address)85 static inline u32 get_mfa_outbound(void __iomem *base_address)
86 {
87 	int retry;
88 	u32 mfa;
89 
90 	for (retry=0; retry<=10; retry++) {
91 		mfa = readl(base_address + OUTBOUND_QUEUE_PORT);
92 		if (valid_mfa(mfa))
93 			break;
94 	}
95 	return mfa;
96 }
97 
set_mfa_outbound(void __iomem * base_address,u32 mfa)98 static inline void set_mfa_outbound(void __iomem *base_address, u32 mfa)
99 {
100 	writel(mfa, base_address + OUTBOUND_QUEUE_PORT);
101 }
102 
get_mfa_inbound(void __iomem * base_address)103 static inline u32 get_mfa_inbound(void __iomem *base_address)
104 {
105 	u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
106 
107 	if (MAILBOX_FULL(mfa))
108 		return 0;
109 
110 	return mfa;
111 }
112 
set_mfa_inbound(void __iomem * base_address,u32 mfa)113 static inline void set_mfa_inbound(void __iomem *base_address, u32 mfa)
114 {
115 	writel(mfa, base_address + INBOUND_QUEUE_PORT);
116 }
117 
get_i2o_message(void __iomem * base_address,u32 mfa)118 static inline struct i2o_message *get_i2o_message(void __iomem *base_address, u32 mfa)
119 {
120 	return (struct i2o_message *)(GET_MFA_ADDR(mfa) + base_address);
121 }
122 
123 #endif /* __IBMASM_CONDOR_H__ */
124